Timing-driven Dragon 

Introduction

    Dragon is a fast, effective standard-cell placement tool for both variable-die and fixed-die ASIC design. It was designed and implemented by NuCAD group in Dept. of ECE, Northwestern University, and ERLAB in Computer Science Dept., UCLA. Dragon does wirelength and routability optimization by combining powerful hypergraph partitioning package (hMetis) with simulated annealing technique. It is a university tool that produces high-quality placement comparable with commercial software such as ITools (formerly TimberWolf) and Cadence QPlace.
 

Features

• Integrating the state-of-the-art partitioner(hMetis), simulated annealing and several other placement techniques (see list of references)
• Solution quality (in terms of total bounding box wirelength) is comparable with mature commercial software.
• Able to handle large circuits (more than 200,000 cells and nets).
• A fast mode is provided to achieve a decent placement quickly.
• Multiple input formats support: GSRC bookshelf, TimberWolf, YAL, LEF/DEF
• Able to handle both variable-die and fixed-die placements
• Timing-driven placement algorithm with physical hierarchy guided slack assignment
   

Results

• Results on GSRC-MCNC benchmarks
• Comparison with Itools on IBM-PLACE benchmarks (Output files)
• Fixed-die placement comparison with Cadence QPlace and UCLA Capo/MetaPlacer

  Download Dragon

    Click here to download executable files (Solaris and Linux)
    Click here to download timing-driven Dragon (executables and benchmarks)

Download IBM-PLACE benchmarks

    This is a set of standard cell placement benchmark circuits with sizes ranging from12,000 to 210,000 modules, derived from ISPD98 IBM benchmark suite. To translate ISPD98 IBM circuits (which are generated for partitioning) into placement benchmarks, we set a fix standard cell height and remove those mega-cells with cell area larger than or equal to 20 times of the minimum area of standard cells. There are two versions of IBM-PLACE benchmarks:

• IBM-PLACE version 1.0
• IBM-PLACE version 2.0

Dragon's results (files) on IBM-PLACE benchmarks
    Click here to download Dragon's outputs on IBM-PLACE (version 1.0) benchmarks

  Related links

• GSRC bookshelf Placement slot
• NuCAD group at Northwestern University
• ER Lab at UCLA
• Labyrinth -- A global router
• hMetis
• ISPD-98 partitioning benchmark suite

  References

  [1] T. Taghavi, X. Yang, B-K. Choi, M. Wang, and M. Sarrafzadeh, "Dragon2005: Large Scale Mixed-Sized Placement Tool".
        International Symposium on Physical Design, ISPD Design Contest, pages. 42-47 IEEE, 2005. [pdf]

  [2] X. Yang, B-K. Choi, and M. Sarrafzadeh, "Timing -Driven Placement using Design Hierarchy Guided Constraint Generation".
        International Conference on Computer-Aided Design, pages. IEEE, November 2002. [pdf] [ps]

  [3] X. Yang, B-K. Choi, and M. Sarrafzadeh, "A Standard-Cell Placement Tool for Designs with High Row Utilization".
        International Conference on Computer Design, pages., September 2002. [pdf] [ps] [full-version(pdf)]

  [4] X. Yang, B-K. Choi, and M. Sarrafzadeh, "Routability Driven White Space Allocation for Fixed-Die Standard-Cell Placement".
        International Symposium on Physical Design, pages 42-47. ACM, April 2002. [pdf] [ps]

  [5] X. Yang, R. Kastner, and M. Sarrafzadeh, "Congestion Reduction During Placement Based on Integer Programming".
        International Conference on Computer-Aided Design, pages 573-576. IEEE, November 2001. [pdf] [ps]

  [6] M. Wang, X. Yang and M. Sarrafzadeh, "Dragon2000: Standard-cell Placement Tool for Large Industry Circuits".
        International Conference on Computer-Aided Design, pages . IEEE, November 2000. [ps] [pdf]

  [7] M. Sarrafzadeh and M. Wang, "NRG: Global and Detailed Placement".
        International Conference on Computer-Aided Design, pages 164-169. IEEE, November 1997. [ps] [pdf]

  [8] X. Yang, M. Wang, K. Eguro and M. Sarrafzadeh, "A Snap-On Placement Tool".
        International Symposium on Physical Design, pages 153-158, ACM, April 2000. [ps] [pdf]

  [9] M. Wang and M. Sarrafzadeh, "Potential_NRG: Placement with Incomplete Data".
        Design Automation Conference, pages 279-282. IEEE/ACM, June 1998. [ps]

  [10] M. Wang P. Banerjee and M. Sarrafzadeh, "Behavior of Congestion Minimization During Placement".
        International Symposium on Physical Design, pages 145-150, ACM, April 1999. [ps] [pdf]

  [11] M. Wang, X. Yang, K. Eguro and M. Sarrafzadeh,
        "Multi-Center Congestion Estimation and Minimization During Placement".
        International Symposium on Physical Design, pages 147-152, ACM, April 2000. [ps] [pdf]

  [12] M. Wang and M. Sarrafzadeh "On Wirelength Prediction Using the Net-cut Objective".
        Submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1999. [ps] [pdf]

  [13] C. Alpert, "The ISPD98 Circuit Benchmark Suite".
        International Symposium on Physical Design, pages 80-85, ACM, April 1998.
 

Last Updated October 2005 .
Page created by Xiaojian Yang ,
currently maintained by Taraneh Taghavi ( taghavi at cs.ucla.edu)