VLSI Physical Design: From Graph Partitioning to Timing Closure
EECS 527 Winter 2013
|| Download Format
|| Multi-threaded Collision Aware Global Routing
|| Impact of Local Interconnects and a Tree Growing Algorithm for Post-grid Clock Distriction
|| A Unified Theory of Timing Budget Management
|| Taming the Complexity of Coordinated Place and Route
|| Accurate Estimation of Global Buffer Delay within a Floorplan
|| Topological Design of Clock Distribution Networks Based on Non-zero Clow Skew Specifications
Related EDA Contests
- ISPD Contests
The International Symposium of Physical Design (ISPD) holds an annual contest
that highlights key problems of the EDA community. Past contests have
dealt with global placement, global routing, and clock tree routing.
The following placers were developed or improved to participate in the 2005 and 2006 Global Placement Contests.
The following placers were developed or improved to participate in the 2007 and 2008 Global Placement Contests.
Starting in 2002, the Special Interest Group of Design Automation (SIGDA)
has organized CADathlon, a one-day programming
competition for graduate students in EDA. Typically, this competition is held the Sunday before the
International Conference of Computer-Aided Design (ICCAD) begins.
Each year, the problems are chosen by a small committee, and written by some of the top experts in
the field. Previous topics have included logic synthesis, timing optimization, placement, routing,