VLSI Physical Design: From Graph Partitioning to Timing Closure
Presentation Materials
Chapter 1: Introduction
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| Chapter 1 Presentation Slides |
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| Chapter 1 Figures (in .ppt format) |
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Chapter 2: Partitioning
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Chapter 2 Presentation Slides Updated 11/17/14 |
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| Chapter 2 Figures (in .ppt format) |
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Chapter 3: Chip Planning
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Chapter 3 Presentation Slides Updated 07/01/13 |
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| Chapter 3 Figures (in .ppt format) |
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Supplemental Materials for Chapter 3
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''B*-Trees and Fast Simulated Annealing'' (unmodified) |
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Chapter 4: Placement
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Chapter 4 Presentation Slides Updated 11/24/14 |
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| Chapter 4 Figures (in .ppt format) |
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Chapter 5: Global Routing
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Chapter 5 Presentation Slides Updated 07/01/13 |
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| Chapter 5 Figures (in .ppt format) |
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Supplemental Materials for Chapter 5
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''FLUTE: Fast Lookup Table Based RSMT Algorithm for VLSI Design'' (unmodified) |
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| ''High-Performance Global Routing with Fast Overflow Reduction'' (unmodified) |
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Chapter 6: Detailed Routing
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Chapter 6 Presentation Slides |
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| Chapter 6 Figures (in .ppt format) |
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Supplemental Materials for Chapter 6
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''What Makes a Design Difficult to Route?'' (unmodified) |
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Chapter 7: Specialized Routing
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Chapter 7 Presentation Slides Updated 07/01/13 |
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| Chapter 7 Figures (in .ppt format) |
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Chapter 8: Timing Closure
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Chapter 8 Presentation Slides Updated 07/01/13 |
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| Chapter 8 Figures (in .ppt format) |
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Supplemental Materials for Chapter 8
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''Sensitivity Guided Net Weighting for Placement Driven Synthesis'' (unmodified) |
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| ''Techniques for Fast Physical Synthesis'' (unmodified) Uploaded 12/06/11 |
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Appendices
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Appendix A Figures (in .ppt format) |
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Appendix B Figures (in .ppt format) |
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