Public Domain Verilog Resources

This site contains public domain design programs for the Hardware Design community.

Tools Native to this site

• Dinotrace - Simulation waveform viewer
• Gspice - Generalized Spice Environment - Characterize cells for Synopsys
• Nicercizer - Keep Solaris nice 19 jobs in the background
• Synopsys-modes - Emacs modes for logfiles, Apollo, Einstimer, Synopsys
• Verilator - Compile Synthesizable Verilog into C code
• Voneline - Convert files to have one Verilog structural instance per line

Tools Native to this site and CPAN

• Make::Cache - Cache Gcc objects for near instantaneous recompiles
• P4::C4 - Perl library for Perforce Revision Management
• Schedule::Load - Perl library for job distribution and status across machines
• SystemPerl - Perl library for SystemC
• Verilog-Perl - Perl library for Verilog Parsing
• Verilog-Pli - Perl library for Verilog PLI Interfacing
• Vpm - Preprocess Verilog Code
• Vregs - Create C and Verilog structures from documentation
• Vrename - Rename signals across Verilog files

Tools co-authored with other sites:

• Verilog-mode - Mac and Wilson's Verilog mode for Emacs

Other Free Tools (other sites)

• PD Cad tool list

• Asynchronous Tools
• U Idaho VLSI Shareware Links

Corporate links & Classes

Books & Other links