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Verilator

Wilson Snyder with Paul Wasson and Duane Galbi

Summary

Verilator is a free Verilog HDL simulator that compiles synthesizable Verilog (not test-bench code!), plus some PSL and Synthesis assertions into C++ or SystemC code. It is designed for large projects where simulation performance is of primary concern.

Do not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial simulator for a little project! Don't get it if you expect a corporate support organization. However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is it.

Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. It also supports very simple assertions and coverage analysis. Verilator supports the more important Verilog 2001 constructs, with additional constructs and Verilog 2005 support added as users request them. Verilator has been used for many very large multi-million gate designs with thousands of modules.

Performance

Verilator does not simply convert Verilog HDL to SystemC. Doing so is fairly easy (and was what Verilator did over 5 years ago). Instead, Verilator compiles your code into a much faster optimized model, which is in turn wrapped inside a SystemC module. The results are a model that executes over 10x faster then standalone SystemC.

Verilator is about 100 times faster then interpreted simulators such as Icarus Verilog. Verilator has about the same performance as the leading commercial simulators including Modelsim, NC-Verilog, VCS and VTOC, but is free, so you can spend on computes rather then licenses. Thus Verilator gives you more cycles/dollar then anything else available. (If you benchmark Verilator, please see the notes in 'bin/verilator' and also let the author know the results; there may be additional tweaks possible.)

Verilog Simulator Benchmarks

Documentation

Online Documentation

Change History/NEWS

Register - Get mail when Verilator gets updated

Verilator SystemC Environment Slides - A paper on using Verilator inside a SystemC environment presented by Wilson Snyder at the 2004 North American SystemC User's Group part of the Design Automation Conference.

Verilator Internals Slides - A presentation on history, usage, and some internals of Verilator presented by Wilson Snyder to Philips Semiconductors in July 2005.

Download

All kits include full sources.

Prerequisites

Verilator should run any system with GCC and Perl. It is developed on 64-bit SuSE 9.3 and other users report success on Redhat Linux, HPUX, Solaris, and Windows NT under Cygwin (C++ only, no SystemC), and Microsoft Visual C++. GLIBC 3 versions (Redhat 9 and newer) have some problems as the SystemC libraries do not yet support that platform, but patches are included in the SystemPerl distribution.

Installation

  • Install Verilog-Perl (Optional, for SystemC output, tracing or coverage)
  • Install SystemPerl (Optional, for SystemC output, tracing or coverage)
  • Ungzip and untar Verilator 
    tar xvzf verilator.tar.gz
  • See README inside the kit for the final make instructions.

See Also

Icarus Verilog - Full featured interpreted simulator

Verilog2Cpp - Compiled Verilator-like simulator

VBS - Verilog Behavioral Simulator

This page maintained by . Copyright © 2005 by W Snyder. All Rights Reserved.