Standard Cells for AMI 0.5um and TSMC 0.25um/0.18um
Welcome! The following pages give information regarding standard cells that were developed for use at the Illinois Institute of Technology. These cells are designed to be used with the Magic and/or Cadence's Virtuoso. The cells are also compatible with the MOSIS
IC prototype fabrication and low volume production endeavor. Please note that we use SCMOS_SUBM rules and not SCMOS.
The library utilizes Synopsys' synthesis tools and Cadence Design Systems' (CDS) Silicon Ensemble Place/Route tool. All of the cells can be viewed and edited using the Cadence Design Systems Virtuoso or the Magic
layout editors. The cell library requires the NCSU design kit
or other design kits available from MOSIS
. A summary of the enhancements that our cell library provides:
- Freely available for all .edu sites
- Mailing list

that provides access to all participants and instant news on possible enhancements and release dates for future generations of the library. - Layouts of the leaf cells
- Characterized for delay and power. Area inserted into Synthesis file for possible area-sensitive synthesis runs.
- Tutorials listed at this site that document step-by-step procedure for users aimed for student use.
- Synopsys synthesis (.db) and Verilog/VHDL simulation libraries
- LEF files for the P&R tool
- All abstracts from CDS' Abstract Generator
- Various drive strengths.
- Documentation that lists power, area, and speed for each device and technology.
- Scripts that automate the procedure and are easy for students to use.
- Scripts that automate insertion and simulation into public-domain and commerical tools.
- Distribution enables Synopsys DesignWare (module compiler) components to be instantiated.
- Verified through MOSIS multiple times with Pad Frame provided by MOSIS.
We also have a mailing list set up to distribute new enhancements and other information that may be pertinent. The mailing list is scells AT ece.iit.edu. If you wish to subscribe to this mailing list, please email James Stine at jstine AT ece.iit.edu and we will be happy to add you to the list. You can also subscribe yourself by emailing scells-request@ece.iit.edu with subscribe in the subject or body of the email. We always strive to improve the cells. Please also note the version number listed below so you can see what version is current.
If you require any clarification, please feel free to contact us. This web page is restricted only to .edu URL's. If you require access to this web page and are not coming from .edu site, please email us to obtain access. These cells are free for educational and non-commerical use. Any commercial use is strictly prohibited.
Note: Any use of these cells for research and/or education must reference the following work:
- J. Grad and J. E. Stine, "A Standard Cell Library for Student Projects," International Conference on Microelectronic Systems Education, IEEE Computer Society, pp. 98-99 2003.
- Poster from MSE 2003 Conference regarding Standard Cells ( pdf

)
Baseline Files
Note Please click email above to email us to get cells. We do this to guarantee the use for non-commercial means and to keep track of its use. We guarantee a short turn-around once an email is placed. We apologize for any inconvenience. In addition, please have the corresponding faculty or person in charge of their project who would like to utilize the cells submit the request. Thank you!Data Sheets (.edu access only)
- We have just posted data sheets created from the characterization CAD tool for each technology. The data values can be useful for assessing the use of these tools for your application. The html files are also included in the baseline distribution above.
Testing
- A low-cost functional tester is available for digital VLSI chips. It is an excellent system designed for University and Commerical firms requiring quick seamless testing. The cells have been verified with this system and is highly recommended. To order or obtain more information, go to the following URL: http://www.onehotlogic.com/


Directory structure
Pad Frame
- The 0.5um cells have a pad frame which can be utilized for fabrication with MOSIS. The pads are fully macro-routable and the basline pads were obtained from Jeff Sondeen's web page (here

). Subsequently, the pads were imported and configured in AbstractGenerator from Cadence Design Systems to obtain the standard-cell interface. In addition, thanks to Jeff for all his help with questions pertaining to the pad design. If you would like to just download the pads, we have them archived here
.
The pads were also modified to fit the 40-pin DIP available through MOSIS. Synopsys' design_compiler automatically instantiates each pad based on its connection. Please note that the power/ground wires are routed but are extremely thin possibly leading to electromigration. Therefore, it would be advisable to expand their width where it connects to the padframe just for safety. In addition, please read the tutorial and links below to prepare the pad frame for simulation through IRSIM. An image of a design with the pad frame is shown below:



Included scripts
- se_shell - Runs Silicon Ensemble in batch mode
- iitcells_se2magic - Script to create a magic layout from Silicon Ensemble output
- iitcells_se2icfb - Script to create a ICFB design from Silicon Ensemble output
- iitcells_cellstats - Script to print statistics on how often each standard cell was used
- iitcells_fixpads - Script to create a valid DIP-40 MOSIS padframe
- iitcells_polyresfix - Script to fix the polysilicon resistor in designs with pads
- iitcells_spice2sim - Script to convert spice file to SIM file for use with IRSIM.
- iitcells_mapperbus - Script to convert a Cadence mapfile (for a flat netlist) to irsim vector definitions istribution
Tutorial and More Information
- It is strongly suggested that you read the tutorial and additional notes before trying to use these cells since there are little bits of information available at the link that may not be intuitively visible. Please note that the tutorial is mainly written for our students who take our VLSI classes. Therefore, much of it may be very simple for those that have experience in VLSI. We apologize for this.
In addition, please note that the tutorial uses a script called gds2mag which is exactly the same as the script in our design flow, however, its called se_shell/iitcells_se2magic. We use the gds2mag convention since its held over from a previous generation of scripts and to maintain conformity.
The TSMC 0.25um VT cells mentioned in the tutorial are from the Virginia Tech distribution available by Professor Dong Ha. The 0.25um libaries we have are different than his, because we utilize SCN5M_SUBM rules, whereas, his addresses SCN5M_DEEP rules. In addition, Professor Ha's cells have different charateristics than ours. Both are useful, however, you can choose the one you like the best. We have both because we believe both are good. To obtain these cells please go his web page
.
The URL is available here: IIT's Place and Route Suport Page

Included Standard Cells
- AND2X1
- AND2X2
- AOI21X1
- AOI22X1
- BUFX2
- BUFX4
- DFFNEGX1
- DFFPOSX1
- FAX1
- FILL
- HAX1
- INVX1
- INVX2
- INVX4
- INVX8
- MUX2X1
- NAND2X1
- NAND3X1
- NOR2X1
- NOR3X1
- OAI21X1
- OAI22X1
- OR2X1
- OR2X2
- TBUFX1
- TBUFX2
- XOR2X1
- XNOR2X1
Copyright © 2001-2003 by the Illinois Institute of Technology. All material appearing on the IIT web servers may not reproduced or stored in a retrieval system without prior written permission of the publisher and in no case for profit.
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
Cadence and Cadence Design Systems are proprietary names and trademarks of Cadence Design Systems. Synopsys is a proprietary name and trademark of Synopsys, Inc.
Contact Information:
VLSI Computer Architecture, Arithmetic, and CAD Research Group
Department of Electrical and Computer Engineering
Illinois Institute of Technology
3301 South Dearbron Street
Chicago, IL 60616
jstine@ece.iit.edu