Index of /~cad/cadence/pads

      Name                    Last modified       Size  Description


[DIR] Parent Directory        15-Jul-2003 19:53      -  
[DIR] icons/                  30-May-2003 16:34      -  
[DIR] magic/                  30-May-2003 16:34      -  
[DIR] sue/                    30-May-2003 16:34      -

Padframes for AMI C5 0.5um (SCN3ME_SUBM) process


Welcome to the Pad Frame for VLSI at the Illinois Institute of Technology brought to you by the wild and wacky VCAC group at IIT!

Portions of the tools here are funded in part by Educational and Research Initiative Fund (ERIF). The available work space within the pad frame is approximatley 2994 lambda x 2994 lambda (roughly 0.9 mm^2). The total size of the chip is 5000 lambda x 5000 lambda (1.5 mm^2).


Note: This padframe has been verified through MOSIS, yet its always good to hear other people's experiences.

These frames are based on ami_release-2001-12-21 as released by J.Sondeen of MOSIS.

Mini_Frame.mag is the original frame from MOSIS.

IIT_Frame.mag is a padframe with all bidirectional cells which gives greater flexibility.

There are Sue schematics for all cells to enable LVS and simulation through the pads.

Additional Info Regarding the Cells and ESD

In the pad frame there are Hi-ESD (Electrostatic Discharge Damage) cells that include a poly-silicon series resistor. Poly-silicon resistors in magic contain "poly" and "prp" shapes (prp is not visible). They are extracted as pfets of type "polyResistor". Ext2sim will not pick those up as resistors but create a pfet with a floating gate terminal. Therefore, a little script that converts polyResistor pfets into "resist" lines in the .ext file. Those are then correctly interpreted by ext2sim as two-terminal resistors. Note that the value is set to constant 100 Ohm for simplicity, which is about what the pads use anyway.

This script is called "polyres_convert" and is in /import/cad1/bin which should be available via your path when you source /import/cad1/scripts/magic.cshrc. It calls polyres_convert.awk for string processing.

How to Run LVS

To run LVS for a design inside a padframe, do this:
  1. Copy all the pads to your directory. It would be recommended that you create a separate and distinct directory for your final assembled layout. That is, keep your functially-correct version of your project in a separate directory and work on copy of it. See your TA if you need help copying your directories. Remember to watch your quotas. To fabricate you will have to simulate through the pads, therefore, place a small piece of metal on the pads with the appropriate label name.
  2. It is important not to move any of the pads too.
  3. Insert your circuit using the :getcell or :dump commands
  4. All Pads must be connected. If you have unused pads, they must be connected to Ground.
  5. For an input pad, connect the Enable to Gnd ring
  6. For an output pad, connect the ENable to Vdd ring.
  7. Connect your Gnd and Vdd rings.
  8. Use your command file from your comlete design and simulate through the pads and verify integrity.
  9. Remember to do the same design in Magic as in the Schematic.
  10. run :ext in magic to create TOPLEVEL.ext file (can take a minute or so). You can also run ext4mag, however, try running on Vulcan to avoid computational lags.
  11. exit magic
  12. Obtain an extraction from your Schematic preferrably in different directories.
  13. run polyres_convert *.ext on your Magic extraction
  14. run ext2sim -R -C TOPLEVEL.ext
  15. run gemini