MARCO GSRC Calibrating Achievable Design: Bookshelf


HARP: Hard-Wired Routind Pattern FPGAs

Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli BozorgzadehLast updated: Mon Jan 03, 2005


Mordern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configurations. However, providing such great flexibility comes at a high cost in terms of area delay and power. HARP is a new routing architecture that has a mixture of hardwired and traditional flexible switches to improve the area, power and performance. Several Benchmarks of the MCNC benchmark suite are routed on a traditional FPGA architecture and the routing profiles of the circuits are analyzed (using the VPR Pattern Finder) to determine the frequency of different HARPs to be used in the switch boxes. The results from the pattern distribution analysis are then used to create a new architecture that has a mixture of flexible and hardwired switches. Finally, the benchmarks are placed and routed on the new architecture and their results compared with the traditional architectures.

HARP is implemented on top of  Power Model to enable power consumption estimation of the HARP architectures.

Source code and executables

Make sure that you read and agree to the terms outlined here before you download.

Complete source code along with benchmark circuits, architecture files and manuals are provided for linux:
download harp's source code. This package includes VPR, TVPack and PowerModel, and our additions to accommodate HARPs.

Command-line options

See the "readme-harp.txt" file provided with the source code.

Data formats and benchmarks

The MCNC benchmarks are provided with the source. HARP pattern frequencies are hardcoded in this version. See notes below on how to change them.

Features and limitations

Performance results

On an average, with the new architecture, delay decreases by about 24%, area by 7% and total power consumption decreases by 8%. For detailed discussions, please refer to the paper below.

Documentation and support


This work is supported in part by NSF under contract CAREER CCF-0347891. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

HARP is implemented on top of Power Model to enable power consumption estimation of the HARP architectures.

Related Tools from Kia Bazargan's Group

Check Kia Bazargan's downloads page.

Link to the Bookshelf FPGA Layout Slot