Kara Poon, Julien Lamoureux, Andy Yan, Steve Wilton, University of British Columbia, S-S. Ang, Wayne Luk, Imperial College
Power dissipation is becoming a major concern for semiconductor vendors and customers. If current design trends continue, a typical microprocessor will consume 50 times more power than that can be supported by cost-effective packaging techniques by 2016. It is clear that power will become one of the two most serious design concerns (along with design complexity) in coming process generations. FPGAs will not escape this trend; already, FPGA vendors report that power consumption is one of the primary concerns of their customers. Compared to ASICs and other custom chips, FPGAs contain long routing tracks with significant parasitic capacitance; during high speed operations, the switching activity on these long routing tracks causes significant power dissipation.
There have been several low-power architectures described in previous works. However, these papers present "point solutions," in that each only considers a single architecture. In order to migrate these low-power techniques to commercial FPGAs, it is critical that researchers be able to estimate power for a wide variety of architectural parameters. To do this, a power model that is flexible enough to target many different FPGA architectures is required.
There have also been numerous CAD algorithms that target low power. Often, these studies rely primarily on reducing switching activity to result in a low-power solution; although reducing switching activity does lower the power, power also depends on the architecture, the lengths of critical signal routes, the rise and fall times of the signals, and the amount of static power. Though neglected in the past, static power is expected to become an increasingly important part of the total power. In order to adequately evaluate these new CAD algorithms and techniques, we have developed a detailed power model to take all these factors into account.
The model contains includes terms for dynamic power, short-circuit power, and leakage power. Although the techniques we employ have been used before, the integration of these techniques into a flexible power model for FPGAs is a novel approach. The model is flexible enough to target FPGAs with different look-up table (LUT) sizes, different interconnect strategies (segment length, switch block type, connection flexibility), different cluster sizes (for a hierarchical FPGA), and different process technologies. As described above, a model such as the one in this paper will become an essential part of any FPGA architect's and CAD tool designer's arsenal.
We have recently enhanced our model. The new version of the model can compute activity values via simulation as well as via stochastic methods.
To download the source code (v1.1), click here .