EDA Tool Flows | ||
Operating System Platform | HDL and Chip Level: Functional Verification, RTL synthesis, mixed standard cell/custom blocks, floorplanning, block place and route | Logic and Physical Levels: Schematic capture, logic level simulation, standard cell place and route, custom layout, physical verification |
Unix | ||
Windows |
Cherrice Traver
Professor of Electrical and Computer Engineering
Union College
traverc@union.edu
Sponsored by the MOSIS Advisory Committee for Education Richard Brown (chair), University of Michigan Don Bouldin, University of Tennessee Dale Edwards, SRC Cesar Pina, MOSIS Cherrice Traver, Union College |