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Charlie Chung-Ping Chen

Charlie Chung-Ping Chen Assistant Professor Extended Homepage Address/E-mail Program Affiliations Courses Education Fields of Interest Publications Awards & Honors Working Experience Summary Files and Links For additional information, see my

Contact Information

3421 Engineering Hall 1415 Engineering Drive Madison, WI 53706

Tel: 608/265-1145 Fax: 608/265-4623 E-mail: chen@engr.wisc.edu

Program Affiliations

• Electrical and Computer Engineering

Courses

• ECE 755: VLSI Systems Design

Education

• PhD 1998, University of Texas at Austin.

Fields of Interest

• Microprocessor VLSI circuit design and optimization
• Full chip-level interconnect synthesis and optimization
• Circuit, interconnect and microwave simulation
• Signal integrity analysis and optimization
• Special circuit design & analysis

Publications

• C. P. Chen, Y. P. Chen, D. F. Wong, "Optimal wire-sizing formula under the Elmore delay model" in Proc. 33th IEEE/ACM Design Automation Conference, 1996
• C. P. Chen, Y. W. Chang, D. F. Wong, "Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation"in Proc. 33th IEEE/ACM Design Automation Conference, DAC 1996
• C. P. Chen, D. F. Wong, "Fast algorithms for optimal wire-sizing under the Elmore delay model" in Proc. ISCAS 1996.
• C. P. Chen, Hai Zhou, D. F. Wong, "Optimal non-uniform wire-sizing under the Elmore delay Model" in IEEE/ACM International Conference on Computer-Aided Design 1996.
• C. P. Chen, D. F. Wong, "Optimal non-uniform wire-sizing formula with fringing capacitance consideration" in Proc. 34th IEEE/ACM Design Automation Conference, 1997
• C. P. Chen, C. Chu, D. F. Wong, "Fast and Exact Simultaneous Wire- and Transistor-Sizing based on Lagrangian Relaxation Method", IEEE/ACM International Conference on Computer-Aided Design, 1998.
• C. P. Chen , N. Menezes, "Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect", VLSI 1998
• C. P. Chen , N. Menezes, "Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching", Proc. 36th IEEE Design Automation Conference, 1999
• C. P. Chen , D.F. Wong, "Error-bounded Pade Approximation via Bilinear Conformal Transformation", Proc. 36th IEEE/ACM Design Automation Conference, 1999

Selected Awards, Honors and Societies

• Design Technology D2000 Award, 1999 Intel Corp.

Working Experience

• 1996-1999, Senior CAD Engineer, Intel Corp.

Summary

High-end microprocessor design is facing challenges from many directions. As the feature sizes shrink to 0.18 micron, the resistance and capacitive and inductive coupling of interconnects increase dramatically. As a result, transistors and interconnects need to be carefully designed together to achieve target performance and maintain signal integrity. As the clock frequency passes 1 gigahertz, the millions of devices become a veritable jungle of microwave elements and timing budgets become very stringent. Traditional design methodologies can no longer survive in the design domain.

My research interests focus on developing breakthrough technologies to enable and facilitate high-end microprocessor design. Currently, I am working on the following topics:

• High-speed circuit design and optimization targeting for high-end microprocessors

• Full-chip level interconnect synthesis and optimization (RLC routing, wire-sizing, repeater insertion, and model order reduction)

• Transistor, interconnect, and microwave simulation and RLC extraction

• Signal integrity analysis and optimization

• Special circuit design and analysis (clock, packaging, power delivery, I/O)

• Optimization methods (mathematical programming and combinatorial optimization)

Files and Links of Interest

• ECE 556 Design Automation Spring 2001
• ECE 755 - VLSI Systems Design
• ECE 902 Simulation, Optimization, and Modeling for VLSI
• ECE756 VLSI CAD Homepage
• ECE902 Simulation, Optimization, and Modeling for VLSI (New Page)
• ICCAD 99 Embeded Tutorial Material
• Temporary ECE 556 First lecture: New file
• VLSI Labs