MARCO GSRC Calibrating Achievable DesignBookshelf

CMU Circuit Benchmarks

Work in progress: last updated Aug 29, 2001

(see other slots)

Herman Schmit

Contents

I. Introduction 
II. Structure of the Benchmarks
III.Designs in the Benchmark Suite
IV. The Goodies

I. Introduction

This slot includes circuit benchmarks for CAD research. It includes a number of benchmarks that are "vertical", meaning that we release the synthesis specification, scripts for synthesis, placement and routing, as well as the resulting netlists, placements and even delay files.

Other designs are also present in this slot, although currently we cannot release the complete vertical design as there are proprietary issues with the libraries, or synthesis specifications.

This is an evolving slot. In coming months, the designs that are not vertical will be "verticalized" by mapping to a publicly available, characterized library that we will also be releasing on this page.

II. Structure of the Benchmarks

The following directory structure is present with all the benchmark designs:
LEFDEF
LEF and DEF files of the placed (and possibly routed design)
bookshelf
bookshelf format of the placed design.
design
includes design documentation, synthesizable and behavioral verilog, testbenches and test suites.
design_scripts
includes design scripts for Synopsys Design Compiler and Cadence Silicon Ensemble.


III. Designs

The following designs are available in the benchmark suite:
CMUDSP_1.0
IDEA1_1.0
IDEA2_1.0
PRChip18_1.0
PRChip35_1.0
picoJava-II_1.0

In addition, a 0.35 micron standard cell library is located in the repository, along with Verilog, SPICE, .lib, .db, and .lef representations.

IV. The Tar Ball!

CMU_Benchmarks_v1.0.tgz

2001, herman@ece.cmu.edu