MARCO GSRC Calibrating
Achievable Design Bookshelf
Executable Placement Utilities
last updated on 03/08/05
Saurabh
Adya , Igor Markov
Contents
I. |
Introduction |
II. |
Executable Utilities
|
III. |
Literature
|
|
I. Introduction
This slot includes executable placement utilities for CAD research.
II. Executable Placement Utilities
- WireLengthCalculator
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. RBPlaceTest1.exe)
- computes center-to-center and pin-to-pin HalfPerimeter
wirelength
given .nodes/.nets/.wts/.scl/.pl files. May also be used to check that
a
set of placement files meets the standard.
CongestionMaps Plotter
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. CongestionMapsTest0.exe)
congestion evaluation and congestion-map plotting for placed
designs.
Use '-help' or '-f filename.aux'
Other options:
-noProb (do not use Probabilistic congestion map)
-plotCongMap base_filename (plot congestion map in
matlab format)
-plotCongMapGP base_filename (plot congestion map in
gnuplot format)
-plotCongMapXPM base_filename (plot congestion map in xpm
format)
- RowIroning Detailed Placer
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. RowIroningTest1.exe)
- Simple Detailed Placer for placed
designs. Uses sliding windows and optimal placement of a small group of
cells.
- Use '-help' or '-f filename.aux'
Other options:
SmallPlacer Parameters
-smPlSkipInitSoln
-smPlAlgo {Branch | DynamicP}
-smPlMinWL {None | HalfRowHeight | RowHeight |
TwiceRowHeight}
-subsetBound <bool>
-smPlStart {Random | Analytic}
-smPlSplit {Random | Even | All}
-plot <filename>
-verb 1_1_1 | silent
Row Ironing Parameters:
-ironPasses <unsigned>
-ironWindow <unsigned>
-ironOverlap <unsigned>
-ironTwoDim
-ironMixed (1D and 2D)
-ironCluster
- Placement Utilities
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. RBPlaceTest4.exe)
- converts from Bookshelf format to LEF/DEF / Plato /
CPlace(IBM) format.
- utility for legalizing a placement by removing overlaps and
snapping cells to site boundaries.
- utility for plotting a placed design in gnuplot format.
- Use '-help' or '-f filename.aux'
Saving options:
-saveAsNodes base_filename
(save in Bookshelf
format)
-saveAsCplace base_filename
(save in Cplace
/ IBM format)
-saveAsPlato base_filename
(save in
Plato / Kraftwerk format)
-saveLEFDEF base_filename
( save in
LEF/DEF format)
-markMacrosAsBlocks (for saveLEFDEF)
-savePl filename
(save the placement in .pl
format/bookshelf)
Misc options:
-legal (Use to remove any overlaps in existing
placement)
-snapToSites (Use to snap cells to sites in
existing placement)
-spaceCellsEqually (for each subrow, space
cells equally)
Plotting options:
-xmin,-xmax,-ymin,-ymax (for plotting range.
Default means all)
-plotNets
base_fileName
-plotNodes
base_fileName
-plotNodesWNames base_fileName
-plot
base_fileName (plots nodes and nets)
-plotWNames
base_fileName (the above + node names)
-plotSites
base_fileName (plots the site map)
-plotNodesWSites base_fileName (the above +
nodes)
-plotRows
base_fileName (plot the rows)
- LEF/DEF to Bookshelf format converter
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. RBPlFromDBTest0.exe)
- converts from LEF/DEF format to Bookshelf format.
- Use '-help' or '-f filename.aux'
Other options:
-saveAsNodes base_filename
(save in Bookshelf
format)
- AutoLayoutGenerator
(Intel Lnx32)
(Intel Lnx64)
(Intel Win32)
(Sparc Sol32)
(a.k.a. RBPlaceTest2.exe)
- produces a layout (.scl and .pl for pads) having specified
aspect-ratio and whitespace. Produces a rectangular layout with
vertically abutting equal-length rows of alternating site orientations
(i.e N, FS, N, FS...)
- BLIF to Bookshelf format
(Generic PERL script)
(Improved version for Linux)
(Improved version for Solaris)
(Improved version for Intel Win32)
- converts from BLIF (SIS) format to Bookshelf format. You can use
the AutoLayout generate to generate a floorplan for the generated
netlist.
- usage of generic version: perl blif2book.pl <blif
file> <output file>
- usage of improved version:
blif2book.exe <blif_file> <output_file> [-options]
Options for the improved versions
-real_size: use more realistic sizes for cells instead of 1x1.
Cell sizes will be generated according to the following rules:
- All cell heights are 1.
- Latches have width 6.
- Inverters have width 1, buffers have width 2.
- 2-input NAND/NOR gates have width 2,
AND/OR/ have width 3, XOR/XNOR have size 5.
- For a cell with N inputs (N > 2)
and B lines in the truth table, the width is B + N.
- Pins are distributed evenly through each cell.
Miscellaneous Scripts
1. Filler Cell Flow (All Platforms)
This script runs the filler cell flow
for low-utilization designs. The placer used in this script is
Capo(MetaPlacer). Disconnected filler cells are added to the design to
reduce the available whitespace to the placer to 10 %. This parameter
can be changed by modifying the parameter
"addDummyNodesPercent" in the
script. The script expects all the benchmark files in
bookshelf format and in
the same directory
usage: runFillerCellFlow basefile_name
2. Mixed-size placement flow by macro-shredding (All Platforms)
This script runs the mixed-size
placemene flow by using the concept of shredding big macros into small
std-cells. The placer used in this script is
Capo(MetaPlacer). The script expects all the benchmark files in
bookshelf format and in
the same directory
usage: runMacroShredFloorplan
basefile_name
3. Convert Bookshelf format placement file to DEF format (All Platforms)
This script converts bookshelf format
placement file to DEF format. Requires an initial def file with proper
information. The script just replaces the placement information for
each node in the components section.
usage: perl
convertPlToDef orig.def placed.pl complete.def
4. Convert Plato(.spc) format placement file into bookshelf
format (All Platforms)
This script converts
Plato/Kraftwerk(.spc) format placement file into bookshelf format.
usage: perl
convertPlatoPl2CapoPl.pl orig.place final.pl
III. Literature
Saurabh N. Adya, Mehmet C. Yildiz, Igor L. Markov, Paul G.
Villarrubia, Phiroze N. Parakh and Patrick H. Madden, "Benchmarking For
Large-scale
Placement and Beyond", International Symposium on Physical Design
(ISPD), pp. 95-103, Monterey, CA, April 2003. (pdf)
Saurabh
Adya and Igor Markov, ”On Whitespace and Stability in Mixed-size
Placement
and
Physical Synthesis”, International Conference on Computer Aided Design
(ICCAD), San Jose, 2003. (pdf)
Saurabh
Adya and Igor Markov, "Consistent Placement of Macro-Blocks using
Floorplanning
and Standard-Cell Placement", International Symposium of Physical
Design
(ISPD), pp.12-17, San Diego,2002. (pdf)