| Faculty | Students | Collaborators |
| Prof. John Hayes | George Viamontes | Prof. Al Aho |
| Prof. Igor Markov | Vivek Shende | Dr. Stephen Bullock |
| Prof. Yaoyun Shi | Smita Krishnaswamy | Prof. Isaac Chuang |
| Hector Garcia | Prof. Shigeru Yamashita | |
| Mailing list: qcircuits@umich.edu (subscribe) | ||
DARPA Quad Chart, (.ppt)
Current Projects
Quantum Computer Architecture and Quantum Design Automation
- K. M. Svore, A. W. Cross, A. V. Aho, I. L. Chuang, I. L. Markov, ``A Layered Software Architecture for Quantum Computing Design Tools'', (.pdf) IEEE Computer, January 2006, pp. 74-83.
Simulation of Quantum Circuits on Classical Computers
- I. L. Markov and Y.-Y. Shi, ``Simulating Quantum Computation by Contracting Tensor Networks'' SIAM Journal on Computing, vol. 38, no. 3, pp.963-981, June 2008.
- G.F. Viamontes, I.L. Markov and J.P. Hayes, ``Equivalence Checking of Quantum Circuits and States,'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 69-74, San Jose, CA, November 2007.
- QuIDDPro: High-Performance Quantum Circuit Simulation
- G. F. Viamontes, I. L. Markov and J. P. Hayes, `` Graph-based Simulation of Quantum Computation in the Density Matrix Representation,'' Quantum Information and Computation, vol.5, no.2 pp. 113-130, February 2005; quant-ph/0403114.
- G. F. Viamontes, I. L. Markov and J. P. Hayes, `` Is Quantum Search Practical?,'' Intl. Workshop on Logic and Synthesis, 2004, pp. 478-485.
- G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Improving Gate-Level Simulation of Quantum Circuits,'' Quantum Information Processing vol. 2(5), October 2003, pp. 347-380.
- G. F. Viamontes, M. Rajagopalan, I. L. Markov, J. P. Hayes, ``Gate-Level Simulation of Quantum Circuits,'' In Proc. of the Asia South Pacific Design Automation Conference, pp. 295-301, January 2003. (PDF) (PS)
- G. F. Viamontes, M. Rajagapolan, I. L. Markov and J. P. Hayes, `` High-Performance Simulation of Quantum Computation Using QuIDDs,'' 6th Intl. Conf. on Quantum Communication, Measurement and Computing (QCMC), July 2002.
Synthesis of Quantum and Classical Reversible Circuits
- V. V. Shende and I. L. Markov, ``On the CNOT-cost of TOFFOLI gates,'' arXiv:0803.2316v1 [quant-ph], March 2008.
- K. Patel, I. Markov, and J. Hayes, ``Optimal Synthesis of Linear Reversible Circuits,'' Quantum Information and Computation, vol. 8, no. 3-4, pp. 282-294, 2008.
- V. V. Shende, S. S. Bullock, I. L. Markov, `` Synthesis of Quantum Logic Circuits,'' IEEE Trans. on Computer-Aided Design, vol. 25, no. 6, pp. 1000-1010, June 2006
- V. V. Shende, S. S. Bullock, I. L. Markov, ``A Practical Top-down Approach to Quantum Circuit Synthesis,'' Proc. Asia and South Pacific Design Automation Conference, pp. 272-275, Shanghai, China, 2005, quant-ph/0406176.
- V. V. Shende and I. L. Markov, `` Quantum Circuits for Incompletely Specified Operators,'', Quantum Information and Computation, vol.5, no.1, pp. 48-57, January 2005, quant-ph/0401162.
- V. V. Shende, S. S. Bullock, and I. L. Markov, ``Recognizing Small-circuit Structure in Two-qubit Operators,'' to APS Physical Review A, 70, 012310, July 2004.
- V. V. Shende, I. L. Markov, and S. S. Bullock, ``Minimal Universal Two-qubit Controlled-NOT-based Circuits,'' APS Physical Review A 69, 062321 June 2004.
- S. S. Bullock and I. L. Markov, ``Smaller Circuits for Arbitrary n-qubit Diagonal Computations,'' Quantum Information and Computation, vol. 4, no. 1, January 2004, pp. 27-47, quant-ph/0303039
- S. S. Bullock and I. L. Markov, `` An Arbitrary Two-qubit Computation In 23 Elementary Gates,'' Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 324-329, Anaheim, CA, June 2003 (BPA nominee). Journal version in APS Physical Review A (012318), vol. 68, no. 1, July 2003.
- I. L. Markov, ``An Introduction to Reversible Circuits'', IWLS, Laguna Beach, CA, May 2003 (invited talk).
- V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Synthesis of Reversible Logic Circuits,'' IEEE Trans. on CAD 22, 710, June 2003.
Circuit Equivalence Checking (Formal Verification)
- G.F. Viamontes, I.L. Markov and J.P. Hayes, ``Equivalence Checking of Quantum Circuits and States,'' Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 69-74, San Jose, CA, November 2007.
Modelling of Faults and Errors in Quantum Circuits
- K. N. Patel, J. P. Hayes and I. L. Markov, ``Fault Testing for Reversible Circuits,'' IEEE Trans. on CAD, 23(8), pp. 1220-1230, August 2004, quant-ph/0404003.
- J. P. Hayes, I. Polian and B. Becker, ``Testing for Missing-gate Faults in Reversible Circuits'', to appear in Proc. Asian Test Symposium, Taiwain, November 2004.