VLSI Physical Design: From Graph Partitioning to Timing Closure
- P. 4 in Chapter 1: the third paragraph makes a seemingly
incorrect claim that placement tools were the first EDA tools used.
- P. 16 in Chapter 1: line 1 "as similar to an FPGA" → "is similar to an FPGA".
- P. 61 in Chapter 3, Fig 3, the slicing trees don't impose any order on the
arrangement of the cut lines, e.g., modules c and d are swapped in the
figure. Thus, generating the floorplan from a slicing tree is ambiguous.
For vertical cuts, the left child should represent the left submodule; for
horizontal cuts, the left child should represent the lower submodule; trees
are evaluated in top-down and left-right manner, and floorplans are
generated from lower-left towards upper-right corner.
- P. 124 in Chapter 4: The legalization of mixed-size netlists that contain
large movable blocks is particularly challenging [4.14] → [4.7].
- P. 143, in Chapter 5, Fig 5.14 "Hanan Points" is missing one Hanan point
at the top.
- P. 186 in Chapter 6: Forbidden pitch rules prohibit routing wires at
certain distances apart, but allows small or greater spacings →
...but allow smaller or greater spacings.
- Chapter 2, slides 30, 33: Cell 1 --> FS(2) and TE(2) are now FS(1) and TE(1).
- Chapter 7, slides 50, 51, 54: Figures 7.17, 7.18, and 7.20 correspond respectively to slides 50, 51, and 54.