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A VLSI FloorplannerAuthors: Saurabh
Adya, Hayward H. Chan, Igor
Markov |
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1.
Recursive
bisection based mixed block placement - group of 6 »
A Khatkhate, C Li, AR Agnihotri, MC Yildiz, S Ono,
… - Proceedings of the 2004 international symposium on Physical …,
2004 - portal.acm.org
Page 1. Recursive Bisection Based Mixed Block Placement Ateen
Khatkhate 1 Chen
Li 2 Ameya R. Agnihotri 1 Mehmet C. Yildiz 3 Satoshi Ono 1 ...
Cited by 32 - Web Search
2.
Fixed-outline
floorplanning: enabling hierarchical design
- group of 10 »
SN Adya, IL Markov - Very Large Scale Integration
(VLSI) Systems, IEEE …, 2003 - ieeexplore.ieee.org
Page 1. 1120 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL.
11, NO. 6, DECEMBER 2003 Fixed-Outline Floorplanning:
Enabling ...
Cited by 33 - Web Search
3.
Floorplanning with alignment and performance constraints
- group of 9 »
X Tang, DF Wong - Proceedings of the 39th conference
on Design automation, …, 2002 -
doi.ieeecomputersociety.org
Page 1. Floorplanning with Alignment and Performance
Constraints £
Xiaoping Tang †‡ and DF Wong † †
University of Texas ...
Cited by 18 - Web Search - BL Direct
4.
Microarchitecture evaluation with physical planning
- group of 13 »
J Cong, A Jagannathan, G Reinman, M Romesis - Proc.
ACM/IEEE DAC, 2003 - doi.ieeecomputersociety.org
Page 1. Microarchitecture Evaluation With Physical
Planning Jason Cong,
Ashok Jagannathan, Glenn Reinman, Michail Romesis Computer ...
Cited by 17 - Web Search
5.
Multi-project
reticle floorplanning and
wafer dicing - group of 12 »
AB Kahng, I Mǎndoiu, Q Wang, X Xu, AZ Zelikovsky - Proceedings of the 2004 international
symposium on Physical …, 2004 - portal.acm.org
Page 1. Multi-Project Reticle Floorplanning
and Wafer Dicing ∗ Andrew B. Kahng,
Ion M˘andoiu † , Qinke
Wang, Xu Xu, and Alex Z. Zelikovsky ‡ ...
Cited by 14 - Web Search
6.
Floorplanning Optimization with Trajectory Piecewise-Linear
Model for Pipelined Interconnects - group of 7 »
C Long, LJ Simonson, W Liao,
L He - Technology - doi.ieeecomputersociety.org
Page 1. Floorplanning Optimization with Trajectory
Piecewise-Linear Model for Pipelined
Interconnects ∗ Changbo Long Lucanus J. Simonson Weiping Liao Lei He ...
Cited by 12 - Web Search - BL Direct
7.
Robust
fixed-outline floorplanning through evolutionary
search
CT Lin, DS Chen, YW Wang - Proceedings of the 2004
conference on Asia South Pacific …, 2004 - portal.acm.org
Page 1. Robust Fixed-outline Floorplanning Through
Evolutionary Search
Chang-Tzu Lin, De-Sheng Chen, Yi-Wen
Wang Department of Information ...
Cited by 8 - Web Search
8.
Fast
floorplanning by look-ahead enabled recursive bipartitioning - group of 7 »
J Cong, M Romesis, JR Shinnerl - Proceedings of the 2005 conference on Asia South
Pacific …, 2005 - portal.acm.org
Page 1. Fast Floorplanning by Look-Ahead Enabled
Recursive Bipartitioning
Jason Cong, Michail Romesis,
and Joseph R. Shinnerl UCLA ...
Cited by 7 - Web Search
9.
Optimal
redistribution of white space for wire length minimization
X Tang, R Tian, MDF Wong - Proceedings
of the 2005 conference on Asia South Pacific …, 2005 - portal.acm.org
Page 1. Optimal Redistribution of White Space for Wire Length Minimization
Xiaoping
Tang IBM TJ Watson Research Yorktown Heights, NY 10598 USA xtang@us.ibm.com ...
Cited by 7 - Web Search
10.
An
area-optimality study of floorplanning - group of 6 »
J Cong, M Romesis, JR Shinnerl - Proceedings of the 2004 international symposium on
Physical …, 2004 - portal.acm.org
Page 1. An Area-Optimality Study of Floorplanning ∗ Jason Cong, Gabriele
Nataneli, Michail Romesis, and Joseph R. Shinnerl
UCLA ...
Cited by 6 - Web Search
11.
Empirical
models for net-length probability distribution and applications - group of 6 »
A Davoodi, V Khandelwal, A Srivastava - Very
Large Scale Integration (VLSI) Systems, IEEE …, 2004 -
ieeexplore.ieee.org
Page 1. 1066 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL.
12, NO. 10, OCTOBER 2004 Empirical Models for Net-Length Probability ...
Cited by 5 - Web Search - BL Direct
12.
IMF:
Interconnect-Driven Multilevel Floorplanning for
Large-Scale Building-Module Designs - group of 2 »
TC Chen, YW Chang, SC Lin - Proc. ICCAD, 2005 - cc.ee.ntu.edu.tw
Page 1. IMF: Interconnect-Driven Multilevel Floorplanning
for Large-Scale
Building-Module Designs Tung-Chieh Chen Graduate
Institute ...
Cited by 5 - View as HTML - Web Search
13.
Temporal
floorplanning using the T-tree formulation
- group of 4 »
PH Yuh, CL Yang, YW Chang -
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM …, 2004 -
ieeexplore.ieee.org
Page 1 0-7B03-8702-31041$20 .00 ©2004 IEEE. 300 Temporal Floorplanning
Using the T-tree Formulation *t Ping-Hung Yuht, Chia-Lin ...
Cited by 4 - Web Search
14.
Modern
floorplanning based on fast simulated annealing
- group of 4 »
TC Chen, YW Chang - Proceedings of the 2005
international symposium on physical …, 2005 - portal.acm.org
Page 1. Modern Floorplanning Based on Fast Simulated
Annealing ∗
Tung-Chieh Chen Graduate Institute of Electronics
Engineering ...
Cited by 4 - Web Search
15.
Constrained
Floorplanning Using Network Flows
Y Feng, DP Mehta, H Yang -
Computer-Aided Design of Integrated Circuits and Systems,
…, 2004 - ieeexplore.ieee.org
Page 1. 572 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS
AND SYSTEMS, VOL. 23, NO. 4, APRIL 2004 VII. C ONCLUSION ...
Cited by 4 - Web Search - BL Direct
16.
Microarchitecture evaluation with floorplanning
and interconnect pipelining - group of 3 »
A Jagannathan, HH Yang, K Konigsfeld, D Milliron, … -
Proceedings of the 2005 conference on Asia South Pacific …, 2005 -
portal.acm.org
Page 1. Microarchitecture Evaluation With Floorplanning And Interconnect
Pipelining Ashok Jagannathan
1 , Hannah Honghua Yang 2 , Kris ...
Cited by 3 - Web Search
17.
Microarchitecture-aware floorplanning
using a statistical design of experiments approach - group of 6 »
V Nookala, Y Chen, DJ Lilja, SS Sapatnekar -
Proceedings of the 42nd annual conference on Design …, 2005 -
portal.acm.org
Page 1. Microarchitecture-Aware Floorplanning
Using a Statistical Design
of Experiments Approach ∗ Vidyasagar Nookala Ying Chen ...
Cited by 2 - Web Search
18.
Mixed
block placement via fractional cut recursive bisection
Agnihotri, A.R. Ono, S. Chen
Li Yildiz, M.C. Khatkhate, A. Cheng-Kok
Koh Madden, P.H.
Comput. Sci. Dept., State
Page 1. 748 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS
AND
SYSTEMS, VOL. 24, NO. 5, MAY 2005 Mixed Block Placement via Fractional ...
Cited by 1 - Web Search
19.
Enhancing
and Using an Automatic Design System for Creating FPGAs
- group of 2 »
Page 1. Enhancing and Using an Automatic Design System for Creating FPGAs by Aaron
Charles Egier A thesis submitted in conformity with
the requirements ...
Cited by 1 - View as HTML - Web Search
20.
A
NOVEL GEOMETRIC ALGORITHM FOR FAST WIRE-OPTIMIZED FLOORPLANNING - group of 9 »
PG Sassone, SK Lim - Proc.
International Conference on Computer-Aided Design, 2003 - sigda.org
Page 1. A NOVEL GEOMETRIC ALGORITHM FOR FAST WIRE-OPTIMIZED FLOORPLANNING
Peter G. Sassone, Sung K. Lim School of Electrical
and ...
Cited by 1 - View as HTML - Web Search - BL Direct
21.
On-line
synthesis for partially reconfigurable FPGAs
- group of 3 »
R Huang, R Vemuri - VLSI
Design, 2005. 18th International Conference on, 2005 - ieeexplore.ieee.org
Page 1. On-Line Synthesis for Partially Reconfigurable FPGAs
Renqiu Huang
and Ranga Vemuri University
of Cincinnati, Cincinnati, OH ...
Cited by 1 - Web Search
22.
ISPD02
Mixed-size Placement Benchmarks
GSRC Bookshelf (see other slots ). ISPD02 Mixed-size
Placement Benchmarks. ...
Cited by 1 - Cached - Web Search
23.
An
Efficient Algorithm to Fixed-Outline Floorplanning
Based on Instance Augmentation
Page 1. An Efficient Algorithm to Fixed-Outline Floorplanning
Based on Instance
Augmentation Rong Liu Sheqin
Dong Xianlong Hong Dept. ...
Web Search
24.
Empirical
Models for Net-Length Probability Distribution and Applications
ADVKA Srivastava -
glue.umd.edu
Page 1. SPECIAL ISSUE FOR SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP) –
GUEST
EDITORS: DENNIS SYLVESTER AND ANDREW KAHNG 1 Empirical ...
View as HTML - Web Search
25.
On
Whitespace and Stability in Physical Synthesis
- group of 3 »
SN Adya, IL Markov, PG Villarrubia
- eecs.umich.edu
Page 1. On Whitespace and Stability in Physical
Synthesis Saurabh N. Adya † ,
Igor L. Markov , Paul G. Villarrubia ‡ †
Synplicity ...
View as HTML - Web Search
26.
Comparing
Simulation Techniques for Microarchitecture-Aware Floorplanning - group of 2 »
V Nookala, Y Chen, DJ Lilja, SS Sapatnekar -
arctic.umn.edu
Page 1. Comparing Simulation Techniques for Microarchitecture-Aware
Floorplanning Vidyasagar Nookala ∗ , Ying
Chen † , David ...
View as HTML - Web Search
27.
Traffic:
A Novel Geometric Algorithm For Fast Wire-Optimized Floorplanning
PG
Page 1. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND
SYSTEMS,
VOL. ??, NO. ??, JANUARY(?) 2005 1 Traffic: A Novel Geometric Algorithm ...
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28.
Physical
design implementation of segmented buses to reduce communication energy
J Guo, A Papanikolaou, P Marchal, F Catthoor - Proceedings of the 2006 conference on Asia South
Pacific …, 2006 - portal.acm.org
Page 1. Physical design implementation of segmented buses to reduce
communication energy Jin Guo 1,2 , Antonis Papanikolaou 1 , Pol ...
Web Search
29.
Simultaneous
floorplanning and resource binding: a probabilistic
approach - group of 2 »
A Davoodi, A Srivastava - Proceedings of the 2005 conference on Asia
South Pacific …, 2005 - portal.acm.org
Page 1. Simultaneous Floorplanning and Resource
Binding: A Probabilistic
Web Search
30.
Simultaneous
Floorplanning and Binding: A Probabilistic Approach
- group of 2 »
A Davoodi, A Srivastava - enee.umd.edu
Page 1. 1 Simultaneous Floorplanning and Binding: A
Probabilistic Approach
Azadeh Davoodi and Ankur Srivastava Department of
Electrical ...
View as HTML - Web Search
31.
IMF:
interconnect-driven multilevel floorplanning for
large-scale building-module designs
Tung-Chieh Chen Yao-Wen
Chang Shyh-Chang Lin, Page
1. IMF: Interconnect-Driven Multilevel Floorplanning
for Large-Scale
Building-Module Designs Tung-Chieh Chen Graduate
Institute ...
Web Search
32.
Simultaneous
Floorplanning and Resource Binding: A Probabilistic
Approach - group of 2 »
Page 1. Simultaneous Floorplanning and Resource
Binding: A Probabilistic
View as HTML - Web Search
33.
Characterization
and Avoidance of Critical Pipeline Structures in Aggressive Superscalar
Processors - group of 4 »
PG Sassone - 2005 -
smartech.gatech.edu
Page 1. Characterization and Avoidance of Critical Pipeline Structures in
Aggressive
Superscalar Processors A Thesis Presented to The Academic Faculty by ...
View as HTML - Web Search
34.
Fixed-outline
floorplanning based on common subsequence
R Liu, S Dong, X Hong - Proceedings
of the 15th ACM Great Lakes symposium on VLSI, 2005 - portal.acm.org
Page 1. Fixed-outline Floorplanning
Based on Common Subsequence Rong Liu
Sheqin Dong Xianlong Hong
Department of Computer Science ...
Web Search
35.
Fixed-outline
floorplanning with constraints through instance
augmentation
RLSDX Hong, Y Kajitani - Circuits and Systems, 2005. ISCAS
2005. IEEE International …, 2005 - ieeexplore.ieee.org
Page 1. Fixed-outline Floorplanning with Constraints
through Instance
Augmentation Rong Liu, Sheqin
Dong 1 , Xianlong Hong Department ...
Web Search
36.
Fundamental
Algorithms for Physical Design Planning of VLSI - group of 2 »
CCN Chu, SW Keckler, PJ McGuinness -
lib.utexas.edu
Page 1. Copyright by Xiaoping Tang 2002 Page 2. The Dissertation Committee
for Xiaoping Tang Certifies that this is the approved version ...
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37.
Minimizing
Wire Length in Floorplanning
X Tang, R Tian, MDF Wong -
Page 1. RC23695 (W0508-095) August 17, 2005 Electrical
Engineering IBM Research
Report Minimizing Wire Length in Floorplanning
Xiaoping Tang ...
Web Search
38.
Fixed-outline
Floorplanning with Constraints through Instance
Augmentation
R Liu, S Dong, X Hong, Y Kajitani - viola.usc.edu
Page 1. Fixed-outline Floorplanning with Constraints
through Instance
Augmentation Rong Liu, Sheqin
Dong 1 , Xianlong Hong Department ...
View as HTML - Web Search
39.
A
Quick Generation Method of Sequence Pair for Block Placement
VS Sunderam… -
Springer
Page 1. VS Sunderam et al. (Eds.): ICCS 2005, LNCS
3516, pp. 954–957, 2005. ©
Springer-Verlag
Web Search
40.
An
Efficient Algorithm to Fixed-Outline Floorplanning
Based on Instance Augmentation
R Liu, S Dong, X Hong - Computer Aided Design and
Computer Graphics, 2005. Ninth …, 2005 - ieeexplore.ieee.org
Page 1. An Efficient Algorithm to Fixed-Outline Floorplanning
Based on Instance
Augmentation Rong Liu Sheqin
Dong Xianlong Hong Dept. ...
Web Search
41.
Modern
Floorplanning Based on B*-Tree and Fast Simulated
Annealing
Tung-Chieh Chen Yao-Wen
Chang, Page 1. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED
CIRCUITS AND SYSTEMS,
VOL. 25, NO. 4, APRIL 2006 637 Modern Floorplanning
Based on ...
Web Search
42.
Heterogeneous
Floorplanning for FPGAs - group of 3 »
Y Feng, DP Mehta - VLSI
Design, 2006. Held jointly with 5th International …, 2006 -
doi.ieeecomputersociety.org
Page 1. Heterogeneous Floorplanning for FPGAs Yan Feng
Department of ECE University
of Minnesota Minneapolis, MN 55455 yanfeng@ece.umn.edu ...
Web Search
43.
Energy/area/delay
trade-offs in the physical design of on-chip segmented bus architecture
- group of 4 »
J Guo, A Papanikolaou, P Marchal, F Catthoor - Proceedings of the international workshop on
System-level …, 2006 - portal.acm.org
Page 1. Energy/area/delay Trade-offs in The Physical Design of On-chip
Segmented
Bus Architecture Jin Guo, Antonis
Papanikolaou, Pol ...
Web Search
44.
Power-driven
simultaneous resource binding and floorplanning: a
probabilistic approach - group of 4 »
A Davoodi, A Srivastava - Very Large Scale Integration (VLSI) Systems,
IEEE …, 2005 - ieeexplore.ieee.org
Page 1. 934 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,
VOL.
13, NO. 8, AUGUST 2005 Power-Driven Simultaneous Resource Binding and ...
Web Search
45.
Unification
of partitioning, placement and floorplanning
- group of 9 »
SN Adya, S Chaturvedi, JA
Roy, DA Papa, IL Markov - Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM
…, 2004 - ieeexplore.ieee.org
Page 1 0-7803-8702-31041$20.00 ©2004 IEEE. 550 Unification of Partitioning,
Placement
and Floorplanning Saurabh N. Adya Synplicity Inc.
Cited by 19 - Web Search
46.
Combinatorial
techniques for mixed-size placement - group of 6 »
SN Adya, IL Markov - ACM Transactions on Design
Automation of Electronic Systems …, 2005 - portal.acm.org
Page 1. Combinatorial Techniques for Mixed-Size Placement SN ADYA and IL MARKOV
University of Michigan, Ann Arbor While recent literature ...
Cited by 14 - Web Search
47.
Engineering
details of a stable force-directed placer - group of 4 »
K Vorwerk, A Kennings, A Vannelli - Computer Aided Design, 2004. ICCAD-2004.
IEEE/ACM …, 2004 - ieeexplore.ieee.org
Page 1 0-7803-8702-3/04/$20.00 ©2004 IEEE. 573 Engineering Details of a
Stable Force-Directed Placer* Kristofer Vorwerk Dept. of ...
Cited by 10 - Web Search
48.
ACG-adjacent
constraint graph for general floorplans - group of 5 »
H Zhou, J Wang - Computer Design: VLSI in Computers
and Processors, 2004. …, 2004 - ieeexplore.ieee.org
Page 1. ACG–Adjacent Constraint Graph for General Floorplans
∗ Hai Zhou and
Jia Wang ECE, Northwestern University, Evanston, IL
60208 ...
Cited by 6 - Web Search
49.
An
improved multi-level framework for force-directed placement - group of 5 »
K Vorwerk, A Kennings -
Design, Automation and Test in
Page 1. An Improved Multi-Level Framework for Force-Directed Placement ∗
Kristofer Vorwerk and
Andrew Kennings Department of E&CE ...
Cited by 5 - Web Search - Library Search
50.
IMF:
Interconnect-Driven Multilevel Floorplanning for
Large-Scale Building-Module Designs - group of 2 »
TC Chen, YW Chang, SC Lin - Proc. ICCAD, 2005 -
cc.ee.ntu.edu.tw
Page 1. IMF: Interconnect-Driven Multilevel Floorplanning
for Large-Scale
Building-Module Designs Tung-Chieh Chen Graduate
Institute ...
Cited by 5 - View as HTML - Web Search
51.
Min-cut
Floorplacement - group of 3 »
JA Roy, SN Adya, DA Papa, IL Markov - to appear IEEE
Trans. on CAD, 2006 - cse.umich.edu
Page 1. To appear in IEEE Trans. on Computer-Aided Design of Integrated
Circuits
and Systems Min-Cut Floorplacement ∗ Jarrod A. Roy ...
Cited by 4 - View as HTML - Web Search
52.
Practical
slicing and non-slicing block-packing without simulated annealing - group of 7 »
HH Chan, IL Markov - Proceedings of the 14th ACM
Great Lakes symposium on VLSI, 2004 - portal.acm.org
Page 1. Practical Slicing and Non-slicing Block-Packing without Simulated
Annealing Hayward H. Chan Igor L. Markov Department of ...
Cited by 4 - Web Search
53.
Temporal
floorplanning using the T-tree formulation
- group of 4 »
PH Yuh, CL Yang, YW Chang -
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM …, 2004 -
ieeexplore.ieee.org
Page 1 0-7B03-8702-31041$20 .00 ©2004 IEEE. 300 Temporal Floorplanning
Using the T-tree Formulation *t Ping-Hung Yuht, Chia-Lin ...
Cited by 4 - Web Search
54.
Modern
floorplanning based on fast simulated annealing
- group of 4 »
TC Chen, YW Chang - Proceedings of the 2005
international symposium on physical …, 2005 - portal.acm.org
Page 1. Modern Floorplanning Based on Fast Simulated
Annealing ∗
Tung-Chieh Chen Graduate Institute of Electronics
Engineering ...
Cited by 4 - Web Search
55.
Floorplan-aware automated synthesis of bus-based
communication architectures - group of 6 »
S Pasricha, N Dutt, E Bozorgzadeh, M Ben-Romdhane - Proceedings of the 42nd annual conference on
Design …, 2005 - portal.acm.org
Page 1. 34.3 565 Floorplan-Aware Automated Synthesis
of Bus-based Communication
Architectures Sudeep Pasricha
† , Nikil Dutt
† , Elaheh ...
Cited by 4 - Web Search
56.
Are
floorplan representations important in digital
design? - group of 7 »
HH Chan, SN Adya, IL Markov - Proceedings of the 2005
international symposium on physical …, 2005 - portal.acm.org
Page 1. Are Floorplan Representations Important In
Digital Design?
H. Chan † , Saurabh N. Adya ‡ and Igor L. Markov † ...
Cited by 4 - Web Search
57.
Temperature
Aware Floorplanning - group of 2 »
Y Han, I Koren, CA Moritz -
Second Workshop on Temperature-Aware Computer Systems (TACS- …, 2005 -
cs.virginia.edu
Page 1. Temperature Aware Floorplanning Yongkui Han, Israel Koren and Csaba Andras
Moritz Department of Electrical and Computer Engineering ...
Cited by 4 - View as HTML - Web Search
58.
Symmetries
in rectangular block-packing - group of 5 »
H Chan, IL Markov - Proc. of the International
Workshop on Symmetry in …, 2003 - eecs.umich.edu
Page 1. Symmetries in Rectangular Block-Packing Hay-Wai
Chan 1 and Igor L. Markov
2 1 hhchan@umich.edu 2 imarkov@eecs.umich.edu Department ...
Cited by 2 - View as HTML - Web Search
59.
Solving
hard instances of floorplacement - group of 4 »
AN Ng, IL Markov, R Aggarwal,
V Ramachandran - Proceedings of the 2006
international symposium on Physical …, 2006 - portal.acm.org
Page 1. Solving Hard Instances of Floorplacement
Aaron Ng, Igor L. Markov
Department of EECS The University of Michigan 1301 Beal ...
Cited by 1 - Web Search
60.
A
fixed-die floorplanning algorithm using an analytical
approach
Y Zhan, Y Feng, SS Sapatnekar - Proceedings of the 2006
conference on Asia South Pacific …, 2006 - portal.acm.org
Page 1. A Fixed-die Floorplanning
Algorithm Using an Analytical Approach
Yong Zhan, Yan Feng, and Sachin S. Sapatnekar Department ...
Web Search
61.
A
comparison of less flexibility first principles with simulated annealing
Page 1. A comparison of Less Flexibility First Principles with Simulated
Annealing *
Shaojun Wei 1,2 , Sheqin Dong 2 , Xianlong Hong 2 ,
Youliang Wu 3 ...
Web Search
62.
A
Case for Thermal-Aware Floorplanning at the Microarchitectural Level - group of 4 »
K Sankaranarayanan, S Velusamy, M Stan, K Skadron -
cs.virginia.edu
Page 1. 1 A Case for Thermal-Aware Floorplanning at
the Microarchitectural Level
Preliminary draft, to appear, Journal of Instruction Level Parallelism 2005. ...
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63.
Application
specific NoC design
L Benini - Proceedings of
the conference on Design, automation and test …, 2006 - portal.acm.org
Page 1. Application Specific NoC Design Luca Benini DEIS Universita di Bologna
lbenini@deis.unibo.it Abstract Scalable Networks on ...
Web Search
64.
A
Fast Placement Approach for Large Scale Modules Based on Less Flexibility First
Principles
S Wei, S Dong, X Hong, Y Wu - ASIC, 2005. ASICON 2005. 6th International Conference
On, 2005 - ieeexplore.ieee.org
Page 1. A Fast Placement Approach for Large Scale Modules Based on Less
Flexibility First Principles * Shaojun Wei1l2, Sheqin Dong2 ...
Web Search
65.
Processing
Rate Optimization by Sequential System Floorplanning
- group of 2 »
J Wang, H Zhou, PC Wu - Quality Electronic Design,
2006. ISQED'06. 7th International …, 2006 - doi.ieeecomputersociety.org
Page 1. Processing Rate Optimization by Sequential System Floorplanning
∗
Jia Wang† Ping-Chih
Wu‡ Hai Zhou† †EECS Department ...
Web Search
66.
Yield-aware
floorplanning - group of 2 »
Z Wo, I Koren,
MJ Ciesielski - Digital System Design, 2005.
Proceedings. 8th Euromicro … -
doi.ieeecomputersociety.org
Page 1. Yield-aware Floorplanning Zhaojun
Wo , Israel Koren, and Maciej J.
Ciesielski Department of Electrical and Computer
Engineering ...
Web Search
67.
How
does partitioning matter for 3D floorplanning?
T Yan, Q Dong, Y Takashima,
Y Kajitani - Proceedings of the 16th ACM Great Lakes symposium on VLSI, 2006 -
portal.acm.org
Page 1. How Does Partitioning Matter for 3D Floorplanning?
Tan Yan Qing Dong
Yasuhiro Takashima Yoji Kajitani Faculty of
Environmental ...
Web Search
68.
Global
lower bounds for the VLSI macrocell floorplanning problem using semidefinite
optimization - group of 2 »
PL Takouda, MF Anjos, A Vannelli -
System-on-Chip for Real-Time Applications, 2005. Proceedings …, 2005 -
ieeexplore.ieee.org
Page 1. Global Lower Bounds for the VLSI Macrocell Floorplanning Problem
using Semidefinite Optimization ∗ PL Takouda, MF Anjos ...
Web Search
69.
Wirelength optimization by optimal block orientation
Page 1. Wirelength Optimization by Optimal Block
Orientation Xin Hao,
Forrest
Brewer Department of Electrical and Computer Engineering ...
Web Search
70.
Heterogeneous
Floorplanning for FPGAs - group of 3 »
Y Feng, DP Mehta - VLSI
Design, 2006. Held jointly with 5th International …, 2006 -
doi.ieeecomputersociety.org
Page 1. Heterogeneous Floorplanning for FPGAs Yan Feng
Department of ECE University
of Minnesota Minneapolis, MN 55455 yanfeng@ece.umn.edu ...
Web Search
71.
Floorplan-aware Bus Architecture Synthesis - group of 3 »
S Pasricha, N Dutt,
Page 1. 1 Floorplan-aware Bus Architecture Synthesis ∗ Sudeep Pasricha†,
Nikil Dutt†, Elaheh Bozorgzadeh† and
Mohamed Ben-Romdhane‡ ...
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72.
Fast
substrate noise-aware floorplanning with preference
directed graph for mixed-signal SOCs - group of 2 »
M Cho, H Shin, DZ Pan -
Proceedings of the 2006 conference on Asia South Pacific …, 2006 -
portal.acm.org
Page 1. Fast Substrate Noise-Aware Floorplanning with
Preference Directed Graph
for Mixed-Signal SOCs Minsik
Cho, Hongjoong Shin and
David Z. Pan Dept. ...
Web Search