| Entry Name: | ABC: A System for Sequential Synthesis and Verification | |
| Groups/PIs: | Alan Mishchenko, Berkeley Logic Synthesis and Verification Group | |
| Status: | available |
| Entry Name: | Logic synthesis: Folded Binary Decision Diagram FBDD | |
| Groups/PIs: | Prof. Jianwen Zhu and Dennis Wu, University of Toronto Synthesis Group | |
| Status: | available |
| Entry Name: | Multi-level logic synthesis: BDS (DAC 2000) | |
| Groups/PIs: | Prof. Maciej Ciezelski at U. Mass Amherst | |
| Status: | ver 1.1 |
| Entry Name: | Heuristic two-level logic minimization BOOM (ICCAD 2001) | |
| Groups/PIs: | Jan Hlavicka and Petr Fiser at Czech Technical University (CTU) | |
| Status: | ver 1.2 |
| Entry Name: | Pass Transistor Logic Synthesizer PTLS (ICCAD 2001) | |
| Groups/PIs: | Rupesh S. Shelar and Prof. Sachin Sapatnekar at the Univ. of Minnesotta | |
| Status: | available |
| Entry Name: | IWLS 2002 benchmark API (+ benchmarks) | |
| Groups/PIs: | Andreas Kuehlman, Cadence Berkeley Labs | |
| Status: | available |
| Entry Name: | ISCAS85/89 and LGSynth89-95 benchmarks | |
| Groups/PIs: | Collaborative Benchmarking Laboratory | |
| Status: | available |
| Entry Name: | Espresso PLA benchmarks | |
| Groups/PIs: | UC Berkeley CAD Group | |
| Status: | available |
| Entry Name: | SIS Example files (including MCNC and ISCAS benchmarks suites) | |
| Groups/PIs: | UC Berkeley CAD Group | |
| Status: | available |
| Entry Name: | Exact and heuristic two-level logic minimization: ESPRESSO | |
| Groups/PIs: | UC Berkeley CAD Group | |
| Status: | available |
| Entry Name: | Exact and heuristic two-level logic minimization: ESPRESSO-ab | |
| Groups/PIs: | UC Berkeley CAD Group | |
| Status: | available |
| Entry Name: | Multi-level logic minimization: MVSIS | |
| Groups/PIs: | UC Berkeley CAD Group | |
| Status: | available |
| Entry Name: | DIADES | |
| Groups/PIs: | Portland Logic Optimization Group | |
| Status: | available |