Slots

Verilog Links and Tools

Circuit and Microprocessor Design Examples

Programming, Software Engineering, Basic Algorithms and Data Structures

Visualization

Scripting and interactive interfaces to EDA tools

VLSI CAD Fundamentals

Generic Optimization: Linear, Non-linear, Geometric, Semi-definite, Quadratic, Mixed Integer-Linear, Multi-objective etc

Decision Diagrams (DDs)

SAT, Integer and Linear Programming

Quantified Boolean Satisfiability and PSPACE-complete problems

Graph Coloring

Computational Geometry

Logic Synthesis

Hypergraph Partitioning

Symmetry-Finding

Vertex/Variable orderings

Block Packing

Wirelength-driven Standard-Cell Placement

Timing Analysis

Signal Delay Calculation

Scan Chain Optimization

Traveling Salesman Problem

Rectilinear Spanning and Steiner Trees (see additional links at the slot page)

Bounded-skew Clock Routing

Grid-based Global and Detail Routing

Single Interconnect Tree Synthesis (SITS)

Clock Skew Scheduling and Clock Topology Generation

FPGA Layout

Gate Sizing

High-Level Synthesis

Standard-cell Libraries

Circuit Modelling

Test Generation

Links to EDA Tools