| Entry Name: | VPR and T-VPack Versatile Packing, Placement and Routing for FPGAs (source code available) | |
| Groups/PIs: | Prof. Vaughn Betz at U. Toronto | |
| Status: | version 4.30 (March 27, 2000) |
| Entry Name: | Altera Embedded System Development | |
| Groups/PIs: | Altera Corporation | |
| Status: | available |
| Entry Name: | Xilinx Design Resources | |
| Groups/PIs: | Xilinx, Inc | |
| Status: | available |
| Entry Name: | TPR: Three-dimensional Place and Route for 3D FPGAs | |
| Groups/PIs: | Cristinel Ababei | |
| Status: | available |
| Entry Name: | HARP: Hard-Wired Routing Pattern FPGAs | |
| Groups/PIs: | Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh | |
| Status: | available |