The PowerPC™ 405 core accesses high speed and high performance system resources through Processor Local Bus (PLB) interfaces on the instruction and data cache controllers. The PLB interfaces provide separate 32-bit address and 64-bit data buses for the instruction and data sides.

The PLB supports read and write data transfers between master and slave devices equipped with a PLB bus interface and connected through PLB signals. Bus architecture supports multiple master and slave devices. Each PLB master is attached to the PLB through separate address, read-data, and write-data buses. PLB slaves are attached to the PLB through shared, but decoupled, address, read-data, and write-data buses and a plurality of transfer control and status signals for each data bus.

Access to the PLB is granted through a central arbitration mechanism that allows masters to compete for bus ownership. This arbitration mechanism is flexible enough to provide for the implementation of various priority schemes. Additionally, an arbitration locking mechanism is provided to support master-driven atomic operations. PLB arbiters can be implemented on the FPGA fabric and are available as soft IP cores. The PLB is a fully synchronous bus. Timing for all PLB signals is provided by a single clock source that is shared by all masters and slaves attached to the PLB.