The PowerPC 405 core accesses low speed and low performance system resources through On-chip Peripheral Bus (OPB). The OPB is a fully synchronous bus that functions independently at a separate level of bus hierarchy. It is not intended to connect directly to the processor core. The OPB interfaces provide separate 32-bit address and up to 32-bit data buses. Since the OPB supports multiple master devices, the address bus and data bus are implemented as a distributed multiplexer. The processor core can access the slave peripherals on this bus through the "PLB to OPB" bridge unit. Peripherals which are OPB bus masters can access memory on the PLB through the "OPB to PLB" bridge unit. OPB arbiters can be implemented on FPGA fabric and are available as soft IP cores. | | |