Homepage - Min Pan

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MIN PAN

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Education Research Resume Publication Interns Contact Links
I am currently a Ph.D. candidate in Computer Engineering from the Department of Electrical and Computer Engineering at Iowa State University.
My research advisor is Dr. Chris C.-N. Chu.

Education:

Ph.D. Candidate, Computer Engineering, Iowa State University, Ames, IA, Aug 2002 ¨C Present

Master of Science, VLSI Design, Tsinghua University, Beijing, P.R.China, 2002.

Bachelor of Engineering, Microelectronics, Tsinghua University, Beijing, P.R.China, 1999.

Research Interests:

Computer-aided design for VLSI circuits. Specifically in Physical Design Field.

¡¤ Extremely Fast Placement Algorithms to handle Power-aware, Timing-driven, and Congestion-driven placement problems for standard cell and Mixed-size designs

¡¤ Efficient Timing-driven, Congestion-driven routing and interconnect optimization techniques

¡¤ Integrated Approach of Placement and Routing

¡¤ Statistical Static Timing Analysis under process variations

¡¤ Low Power VLSI Design Methodology and Low Power Clock Network Synthesis

Resume:

.pdf
.ps

Recent Publications:

¡¤ Min Pan and Chris Chu, FastRoute 2.0: A High-quality and Efficient Global Router. Asian and South Pacific Design Automation Conference, 2007.

¡¤ Min Pan, Chris Chu and Priyadarsan Patra, A Novel Performance-Driven Topology Design Algorithm. Asian and South Pacific Design Automation Conference, 2007.

¡¤ Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. Asian and South Pacific Design Automation Conference, 2007.

¡¤ Min Pan and Chris Chu, FastRoute: A Step to Integrate Global Routing into Placement. IEEE/ACM International Conference on Computer-Aided Design, pages 464-471, 2006.

¡¤ Natarajan Viswanathan, Min Pan and Chris Chu. FastPlace 2.0: An Efficient Analytical Placer for Mixed-Mode Designs. In Proc. Asia and South Pacific Design Automation Conference, pages 195-200, 2006.

¡¤ Min Pan, Natarajan Viswanathan and Chris Chu. An Efficient and Effective Detailed Placement Algorithm. In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 48-55, 2005.

¡¤ Natarajan Viswanathan, Min Pan and Chris Chu. An Efficient Analytical Placement Algorithm for Mixed-Mode Designs in the Presence of Placement Blockages. In Proc. SRC TECHCON2005, Oct., 2005.

¡¤ Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace: An Analytical Placer for Mixed-Mode Designs In Proc. Intl. Symp. on Physical Design, pages 221-223, 2005.

¡¤ Min Pan, Chris Chong-Nuen Chu and J. Morris Chang, Transition Time Bounded Low-Power Clock Tree Construction. In Proc. IEEE Intl. Symp. Circuits and Systems, 2005.

¡¤ Min Pan, Chris Chong-Nuen Chu and Hai Zhou, Timing Yield Estimation Using Statistical Static Timing Analysis. In Proc. IEEE Intl. Symp. Circuits and Systems, 2005.

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¡¤ Min Pan, Natarajan Viswanathan and Chris Chu. An Efficient and Effective Detailed Placement Algorithm. Submitted to IEEE Trans. on Very Large Scale Integratation Systems.

¡¤ Min Pan, Chris Chu and Hai Zhou. Timing Yield Estimation under Process Variations Using Statistical Static Timing Analysis. Submitted to IEEE Trans. on Computer Aided Design of Large Scale Designs.

Interns:

Intel Corporation, Hillsboro, OR.

Intern at Strategic CAD Labs, Design and Technology Solutions, TMG May 2005 ¨C Aug 2005

Research on Power-aware, Timing-driven and Congestion-driven global routing problem at SCL. Developed an unconventional Topology design tool which could generate Steiner tree topologies very fast with good power, timing and congestion on ARs. The algorithm has various applications in the physical synthesis flow such as Placement, Global Routing and Interconnect Optimization.

Micron Technology, Inc., Boise, ID.

CAD Engineer in CMOS Imaging Dept. May 2004 ¨C Aug 2004

Designed the DRC Rules Tester for the Cadence design environment using SKILL. The tester reads in the spreadsheet which defines the DRC rules parameters and automatically generates tester shapes for the DRC rules. After running the DRC checking, the tester can give out the report for the errors in DRC rules.

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Contact Information:

Email: panmin@iastate.edu
Web: http://panmin.public.iastate.edu/
Office: 337 Durham
Phone: (515) 294-7706

¡¤ Mailing address:

            Min Pan
            Graduate Research Assistant
            Department of Electrical and Computer Engineering
            Iowa State University
            2215 Coover Hall
            Ames, IA 50011-3060