Welcome to my homepage ... |
Research | Publications | Resume | Contact Information | Links |
This page will always be under construction !!! |
I am currently pursuing my Ph.D. in Computer Engineering from the Department of Electrical and Computer Engineering at Iowa State University. My research advisor is Dr. Chris C.-N. Chu. Presently, I am a long-term Technical Co-op at IBM Austin Research Lab working on the Placement Driven Synthesis flow within IBM. |
Large-scale integrated floorplanning and placement
Efficient and Scalable Algorithms to handle Congestion-driven and Timing-driven placement
Fast Timing Optimization techniques
Development of an Integrated Placement and Timing Optimization Framework
Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren and Chris Chu, RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. In Proc. Design Automation Conference, pages 453-458, 2007. (Nominated for DAC Best Paper Award)
Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control. In Proc. Asia and South Pacific Design Automation Conference, pages 135-140, 2007.
Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace 2.0: An Efficient Analytical Placer for Mixed-Mode Designs. In Proc. Asia and South Pacific Design Automation Conference, pages 195-200, 2006.
Min Pan, Natarajan Viswanathan and Chris Chu, An Efficient and Effective Detailed Placement Algorithm. In Proc. IEEE/ACM International Conference on Computer-Aided Design, pages 48-55, 2005.
Natarajan Viswanathan, Min Pan and Chris Chu, An Efficient Analytical Placement Algorithm for Mixed-Mode Designs in the Presence of Placement Blockages. In Proc. SRC TECHCON 2005, Oct. 2005.
Natarajan Viswanathan, Min Pan and Chris Chu, FastPlace: An Analytical Placer for Mixed-Mode Designs. In Proc. International Symposium on Physical Design, pages 221-223, 2005.
Natarajan Viswanathan and Chris Chong-Nuen Chu, FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model. In Proc. International Symposium on Physical Design, pages 26-33, 2004. (ISPD 2004 Best Paper Award)
FastPlace: An Analytical Placer for Large-scale VLSI Circuits
ISPD04 IBM Standard Cell Benchmarks with Pads (IBM benchmarks used in the ISPD-2004 FastPlace paper)
Bookshelf slot with links to various Placement Algorithms and Benchmarks
Background from GRSites.com
Last modified: Jun 11, 2007