This IP consists of a fully programmable, one cycle Huffman decoder suitable for the hardware implementation of the JPEG algorithm. The core also supports restart markers. The size is about 7000 gates plus about 5 Kbits of one port RAM for both luminance and chrominance.
Speed is in excess of 75 MHz in 0.25 u process. This core is available now. Download the Huffman Decoder flyer. | 
