Design for Quality in the Era of Uncertainty

The 7th International Symposium on Quality Electronic Design, ISQED 2006 is a premier Design and Design Automation conference, held in technical sponsorship of IEEE EDS, IEEE CPMT, and in cooperation with IEEE CASS, ACM/sigDA. ISQED is the pioneer and leading conference dealing with design for manufacturability, design for yield, design for reliability, and design for quality issues, front to back. The ISQED'06 conference spans three days, Monday through Wednesday, in three  parallel tracks, hosting near 100 technical presentations, six keynote speakers, two panel discussions, workshops /tutorials and other informal meetings. Conference proceedings are published by IEEE Computer Society. Proceedings CD ROMs are published by ACM. In addition, continuing the tradition of reaching a wider readership in the IC design community, ISQED will continue to publish special issues in leading journals. The authors of high quality papers will be invited to submit an extended version of their papers for the special journal issues.

Call for Papers

The International Symposium on Quality Electronic Design (ISQED), is a premier Design & Design Automation conference, aimed at bridging the gap between and integration of, electronic design tools and processes, integrated circuit technologies, processes & manufacturing, to achieve design quality. ISQED is the pioneer and leading conference dealing with design for manufacturability and quality issues. The conference provides a forum to present and exchange ideas and to promote the research, development, and application of design techniques & methods, design processes, and EDA design methodologies and tools that address issues which impact the quality of the realization of designs into physical integrated circuits. ISQED emphasizes a holistic approach toward design quality and intends to highlight and accelerate cooperation among the IC Design, EDA, Semiconductor Process Technology and Manufacturing communities.

Designers of the Integrated Circuits & Integrated Systems (IP , SoC, SiP)

Researchers, Developers, and Users of  EDA/TCAD Tools & Design Methodologies

Process/Device Technologists, and Semiconductor Manufacturing Specialists

 

 

Views on Design Quality Summary of Past ISQED Keynote Speeches

Slap It Together And Ship It! Aart J. de Geus Chairman & CEO, Synopsys Inc. In today’s world of e-commerce and dot-com instant business successes, time to market constraints have taken the upper hand in almost all product decisions. In that scenario, what happens to the role of quality in the design of semiconductors and electronic systems? In this keynote, Aart de Geus addresses the trade-offs of “market” needs vs. “quality” needs and shows that what appears to be a trade-off may not be one at all.   The Practical Side of Quality John East CEO, Actel Corporation My practical definition of quality is getting it right the first time, on time. The downsides of poor quality work need no explanation. Unfortunately, though, the consequences of being late to market can doom any potential market advantage. The only sure win comes when the product is both high quality and on time. To help assure on-time delivery of working ICs, I advocate “two-handed management.” This means with one hand, do the job as best you can using the tools and techniques available, but with the other hand, take steps to see similar jobs are done better and faster the next time. An example of twohanded management in the distant past was the development of various simulation techniques. The two-handed manager of the future will look for silicon with advanced capabilities in the areas of “observability,” “tweakability” and incremental specification techniques as well as inherent improvements in speed, power and cost.   Design for Quality and Manufacturing Prakash Agrawal CEO, NeoMagic This presentation will discuss from a CEO’s perspective the process needed to design a quality chip for manufacturing. It will cover the milestones necessary for bringing a successful chip to market. Discussion highlights will focus first on a well thought out analysis of market requirements, taking into account the product roadmaps and feature requirements of your major customers, the competition, the potential market size, and the delivery schedule necessary to hit the window of opportunity to sell the new product. Next, it will focus on how to proceed with a thorough evaluation of your company’s internal variables, such as your technology roadmap, cost analysis, capability of strategic partners, capacity requirements, and return on investment. Finally, it will give tips on evaluating the results of matching the market requirements with your company’s internal capabilities. It will mention some of the well-known design tools and practices used in the industry that can help you assure the built-in quality necessary to meet manufacturing standards and market needs.     Ramping New IC Products in the Deep Sub-micron Age John Kibarian CEO, PDF Solutions It is well known that the majority of the potential profits are early in a products life. This is especially true in product segments such as system on a chip, graphics accelerators, microprocessors, and memory. The spoils in these segments go the company who gets its product to market first. At the same time, the investments required to produce the next generation products is going up at an accelerated pace. As a result, companies are sharing the investment by working with more third party suppliers. Today, a chip will be designed with 3rd party EDA tools and using commercial IP. It is often manufactured in commercial foundries, and tested and assembled a separate company. When the product is not meeting yield and performance, how are the issues resolved? Eventually, these yield issues are resolved, but often not before the profitable part of the product’s lifecycle is complete. In this presentation we describe new methodologies, tools and services which can help turn designs into products. We will summarize the key technical issues which make performance and yield targets difficult to meet given the product’s lifecycle constraints and demonstrate how these new methodologies can greatly change the production ramp. Examples of these methods applied to advanced products such as microprocessors, embedded DRAM, and system on a chip, and DRAM will be provided.   Platform-based Design: A Path to Efficient Design Re-Use Alberto Sangiovanni-Vincentelli Prof., UCB System design is undergoing a series of radical transformations to meet performance, quality, safety, cost and time-to-market constraints introduced by the pervasive use of electronics in everyday objects. An essential component of the new system design paradigm is the orthogonalization of concerns, i.e., the separation of the various aspects of design to allow more effective exploration of alternative solutions. Since the mask set and design cost for Deep Sub-Micron implementations is predicted to be overwhelming, it is important to find common architectures that can support a variety of applications. In this talk, we will explore methods for selecting families of software and hardware architectures that allow a substantial design re-use and some paradigms for embedded system designs that are likely to become the pillars of future tools and flows.   Embedded-Quality for Test Yervant Zorian Chief Technology Advisor, LogicVision The basic concept of embedding test functions onto the very IC design is a simple one. However, the complexity offered by the emerging system-on-chip and the very deep micron technologies has created difficult challenges and quality risks. A new wave of embedded, quality insurance functions, are needed to address this complexity level. This talk will discuss such design for quality trends and solutions and will analyze their impact not only on go/no-go test, but also on a set of expanded quality insurance functions to support debug, measurement, diagnosis and repair.   Deep Submicron ULSI Design Paradigm: Who is writing the future? Kamran Eshraghian Prof., Edith Cowan University The concept of “ technology generation” attributed to Gordon Moore has created a plausible method for predicting the behavior of technology road map that has seen world’s production of silicon CMOS to exceed 75% of electronic related materials. A feature of such progress is characterized by the complexity factor that predicts the emergence of a new generation of technology every three years. A reasonable method of comparison would be to observe the parallel between CMOS based systems with those of biologically inspired systems. Deep submicron, synonymous with Ultra Large Scale of integration, suggests that by the year 2010 the number of transistors/chip will be in the order of 0.5x109, with an intrinsic clock speed of 3GHz. At this level of integration the classic MOS transistor would have only a few ‘electrons’ in the channel to direct. Thus, the reality of Quantum MOS (QMOS) transistor becomes a plausible possibility. In the mean time the question remains as to how are we going to cope with the design and quality of the new system complexity. ULSI design requires a shift in the design paradigm from current evolutionary thinking for system integration, to more of revolutionary approaches as depicted by attributes of “brain architecture”.   Future Platform for Mobile Communication Hajimi Sasaki Chairman of the Board, NEC This keynote would explore three driving forces in the IT revolution that are actualizing an Information Society: first, the Internet global, ever expanding nature and second, the ability to create the ultimate personal information tool. And last, at the heart of these forces is the cutting-edge semiconductor device. Especially in mobile where products are composed primarily of semiconductors, we see that the creation of advanced semiconductor devices controls to a large degree the superior nature of the mobile product. Mobile products must balance many constraining criteria such as size and weight against functionality such as low power consumption. There are also a wide array of technologies involved such as low power consumption circuit design, flash memory and RF power device. Additionally, intellectual property has become even more important. Moreover, the harmonization of semiconductor technology and peripheral technologies such as smallscale, light-weight packaging technology, long life rechargeable batteries and flat panel displays has become an important factor.   Delivering Quality Delivers Profits Joe Costello CEO, think3 The future of electronics is SoC design. SoC design complexity is accelerating due to rapid change on multiple dimensions: design content, deep sub-micron (DSM) electrical and physical effects, and the sheer scale of SoC projects. At the same time, market windows are dramatically decreasing. These fundamental technology trends and economic forces underscore the need to rethink conventional design methodology and conventional business practices for SoC design delivery. An SoC design foundry, combining a fast and scalable mixed-signal SoC design methodology with innovative design technology and electrical engineering expertise, enables not only the timely delivery of SoC designs, but also robust design quality through electrically correct silicon engineering.   The Expanding Use of Formal Techniques in Electronic Design Raul Camposano CTO/GM, Synopsys, Inc. Although Electronic Design Automation (EDA) tools allow some tolerance for features having only limited scope or not working in all cases, there is no tolerance for error in their final results. Since the beginning, EDA tools have included so-called "formal" techniques to ensure such error-free results. More and more, formal verification tools are being adopted as a necessary part of mainstream design flows to tackle the exploding verification challenge. In this keynote address, we will focus on some of these formal techniques; in particular, equivalence checking, property checking, and the combination of simulation with formal techniques -- all of which play an important role in creating zero-defect results in state-of-the-art electronic design.   IC Design Methodology in the Foundry Era: Introducing ‘Heads-Up’ Design” Edward C. Ross President, TSMC, USA The emergence of the foundry as a primary semiconductor manufacturing resource has created a seachange in the way EDA companies interact with manufacturers. Since the key concern for many foundry customers is time-to-volume, EDA companies are now focused not just on system-level design, but on “heads-up” design, e.g., bringing to designers the ability to build whole systems at the speed of thought. Dr. Ross discusses emerging trends in the EDA, IP, library and design center communities, wherein deep collaboration with foundries is producing a variety of Internet-based solutions that are revolutionizing IC design methodologies.   Quality of Design from an IC Manufacturing Perspective Wojciech P. Maly Professor, Carnegie Mellon University There are many credible sources (including the ITRS) now seeing cost of IC manufacturing as a potentially negative factor that may affect the future of the IC industry. There are also a number of answers to the growing-cost-of-manufacturing challenge. One of them is IC design for efficient manufacturing -- measured by such indices as yield, time-to-volume, etc. The first objective of this presentation is to analyze publicly discussed visions for the IC industry and derive from them manufacturability conditions that must be met for these visions to materialize. We will focus our discussion on the recent version of the ITRS. It will be shown that ITRS predictions cannot be fulfilled by design or manufacturing approaches alone. Only by solving complex trade-offs on the design-test-manufacturing interface one may provide a chance to overcome the rising-cost-of manufacturing problem -- the main stumbling block on the ITRS horizon. The second objective of the presentation is to propose a redefinition of the notion of the quality of IC design, so it can accommodate manufacturability measures as primary design goals in addition to traditional die size, performance and time-to-first-silicon design quality indices. Such a re-definition is possible and maybe necessary contribution of the IC design community in addressing the rising-cost-of manufacturing problem.   Embedded Test Leads to Embedded Quality Vinod Agrawal CEO, Logic Vision The concept of embedded test, wherein physical test engines are built right on to the semiconductor chip, has a very strong quality value throughout the lifecycle of the chip. These embedded testers can be reused throughout the lifetime of the chip from silicon debug, to characterization, to production testing (both wafer probe and final test), to board prototyping, to system integration and then finally to the diagnosis in the field. More than 50 semiconductor and system companies world-wide are already using embedded test in their complex chips, to gain significant quality, cycle time and economic competitive advantage. This talk will explore how embedded test is becoming a standard choice for IC and system developers.   Quality on Time Aki Fujimura COO and President, Simplex How is it that a group of talented, highly motivated, hard-working software engineers consistently produce low-quality software, late? It is the speaker's view that schedule management and quality management go hand in hand. The traditional thinking that quality and schedule are tradeoffs is exactly the approach to engineering management that starts the downward spiral resulting in organizations that can never deliver quality software nor on-time delivery. The talk discusses the notion that schedules are probability distributions, and presents several practical quality and schedule management techniques.   Quality of SoC designs through quality of the design flow: Status and Needs Philippe Magarshack Vice President, Central R&D Group and Director, Design Automation, STMicroelectronics It is now universally recognized that System-on-Chip (SoC) is the appropriate product solution to meet the demand of cost and volume for many electronics markets. The increasing pressures coming from shrinking market windows, accelerating process roadmaps and increasing mask costs, render necessary that SoC be correct at first silicon. This is becoming a considerable challenge due to the complexity of systems that can be built on the same chip: current process capabilities are approaching 100 million devices. Additionally, this level of integration comes at the price of renewed parasitic effects, such as crosstalk, voltage drop and electro-migration. A complex design flow is necessary to solve these conflicting trends, combining executable specifications, isolating function from communication, exploring architectures and trading off speed, power, area and schedules, and finally a fast route to implementation, be it in software running on embedded processors, dedicated digital hardware, or dedicated analog cells. The successive levels of abstraction of the system description warrant the need for extensive verification of the SoC, both at functional level, and at the timing, power and reliability levels. Building such a design flow calls for mixing very good point tools, coming from established EDA vendors as well as start ups and academia. But above all, it requires well-defined and structured interfaces between tools at key hand-off points in the design flow. Standard design languages and Application Programming Interfaces (API's) are fundamental to the success of SoC.     IP REUSE QUALITY: “Intellectual Property” or “Intense Pain”? John Chilton Sr. VP and General Manager Synopsys, Inc. As systems on a chip become more complex, reuse of third-party intellectual property (IP) becomes more necessary to meet time-to-market deadlines. However, issues surrounding IP quality are very much unresolved. Poor IP quality is the key reason why many IP users feel that “IP” is actually an acronym for “Intense Pain.” . There are major inconsistencies surrounding basic quality, including fully synchronous design, registered inputs and outputs for IP blocks, and completion of full specifications before design. All these inconsistencies contribute to difficulties in using the IP and integrating it into a chip design. One of the key reasons why quality is still such an issue within the IP community is the issue of “reuse” versus “salvaging.” Much of the IP sold over the last few years wasn’t really designed for reuse. Instead, it was designed for use in a single chip, then later repackaged (i.e., salvaged) as IP. There has also been tremendous interest in creating IP repositories—fancy Java based, Web-accessed, and multi-featured custom products meant to hold the wealth of IP. Along the way, though, we forgot to create enough fully reusable IP to warrant these repository investments. Although the challenges in the IP business may seem daunting (and there are many more besides just those that concern quality), they are well worth the effort when you consider the rewards. There’s a tremendous need for IP to address the growing productivity gap, which represents a great opportunity for the third-party IP industry.   Why Integrated Yield Management is a Necessity Y. David Lepejian President, CEO and Chairman HPL Improving semiconductor yield is a multi-facetted process that must include design, manufacturing, and test. An integrated approach enables companies to rapidly reach higher levels of revenue and profitability. Incorporating design-for-yield concepts early, improving the quality of the test programs, and applying new technology to accelerate the measurement and correction of failure sources in the production process combine to have powerful effect upon company profits, product quality, and time to volume.   Design Success: Foundry Perspective Jim Kupec President, UMC USA Leading edge foundries are rolling out new process technologies every two years with today’s advance processes capable of producing a quarter billion transistor on a thumb nail sized chip. The growth of the fabless business model has enabled many companies to organize and build value with the strength of their design capabilities. Quality is often reflected by the continued success of design practices resulting in market success. The many styles of design implementations provided by a large number of companies sharing a common process helps provide a Darwinian view of quality practices. The interaction with design flows, libraries, special purpose IP, memory types are important considerations. This talk will address the trade-offs and successful design technologies used in foundries.   What you don’t know CAN hurt you: Designing for survival in a sub-wavelength environment Y.C. (Buno) Pati President and CEO, Numerical Technologies The semiconductor industry’s promise to deliver an endless array of chip designs to match the voracious appetite for smaller, faster, cheaper devices is in danger of ringing hollow. We could make this commitment with confidence up to recently. But, lately we’ve hit the wall. We’re crashing through the sub-wavelength barrier and we’re feeling our way toward designing and manufacturing chips in a challenging new environment without benefit of some key process technologies. Now, to survive and thrive, chipmakers are turning to phase shifting—just a novel, clever concept a few short years ago—as a critical and necessary enabler of producing integrated circuits at dimensions of 0.13 micron and below. Inevitably, chip designers are following suit, not just to match the chipmakers in their march to smaller feature sizes, but to polish their own competitive edge with high-performance chip designs that are easy to produce. They’re breaking out of a somewhat isolated mold, knowing that shrinking design times and increasing layout complexity call for new tools and expertise. Most acknowledge that the success of their designs, and indeed, their future viability depends on quickly adopting the tools and expertise that their chip making customers are using so effectively.   The Role of ICs in the Creation of a Connected World and the importance of Product Quality Atiq Raza Chairman and CEO, Raza Foundries Inc. Human Beings being social have had a need to communicate. The modem chapter in enabling large-scale communication has been aided by intelligence in the transport, distribution, protection, traffic management, decoding, analyzing and displaying of communication content. The intelligence has been embedded in an explosive confluence of Software, Systems and Integrated Circuits. This has resulted in the most amazing transformation of the way we live our lives, work, and engage in all other necessary and capricious activity. It has also created a huge economic footprint on the Gross Domestic Product of the United States of America. With a massive transformation that has occurred in such a short time, this throbbing network across the planet has to operate reliably because of the precious payload it carries.   Wireless Systems-on-a-Chip Design Bob Brodersen Dept. of EECS, University of California, Berkeley There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links is also rapidly evolving. The multiple inter-related technologies required for implementation of such wireless systems requires a co-design strategy in communication algorithms, digital architectures as well the analog and digital circuits required for their implementation. Critical to good design of these chips is the definition of energy and area performance metrics that can facilitate the tradeoff of issues such as the cost of providing flexibility or the amount of parallelism to exploit. These design decisions can result in differences of orders of magnitude in the metrics between what is possible in the technology and what is often achieved if the costs are not fully understood. A design infrastructure which supports architectures, which optimizes the metrics, will be described for wireless systems that provides a fully automated chip design flow design flow from a high level system specification.   Microwave III-V Semiconductors for Telecommunications and Prospective of the III-V Industry Chan Shin Wu President & CEO WIN Semiconductors The Microwave m- v semiconductor IC technology (Primarily GaAs) has emerged as a powerful, enabling, technology for the wireless and optical communications in the past 5 years. It has been dominating, or making substantial penetration into, the market for handset power amplifiers and switches, advanced wireless LAN RF front-ends and various other key RF components for broadband wireless, wireless infrastructure, satellite telecommunications, high data rate fiber optical communications and automotive radar applications. The Microwave III-V semiconductor IC industry has grown dramatically in the past 2-3 years. It is worth noting that the majority of the recently formed GaAs Fabs are located in Taiwan. Their intent is to provide pure-play foundry services following the silicon foundry business model developed by TSMC and UMC. In this presentation, we will discuss the key components of III-V microwave transistors (HBT, pHEMT and MESFET etc.) and their RFICs/MMICs, their electrical performance, major applications, market status, trends and opportunities. We will define the current status for the global m-v semiconductors industry, the rapidly growing GaAs MMIC Fab industry in Taiwan and its advantages for providing a one-stop, total solution for the wireless and optical communication components customers.   Tomorrows High-quality SoCs Require High-quality Embedded Memories Today Ulf Schlichtmann Senior Director, Infineon Technologies AG Embedded memories increasingly dominate SoC designs -whether chip area, performance, power consumption, manufacturing yield or design time are considered. ITRS data indicate that the embedded memory contents of ICs may increase from 20% in 1999 to 90% at the SOnm node by the end of the decade. Therefore, even more than today, the success of tomorrow's SoC design will depend on the availability of high-quality embedded memories. Advanced process technologies pose new challenges for meeting these quality criteria. Some of the challenges are: providing flexible redundancy solutions for embedded SRAMs; designing competitive memories despite ever increasing leakage currents; reducing SRAM susceptibility to soft-error rate (SER). These challenges are bringing about the need for significant innovations in design of embedded memories, much more so than in recent previous process generations. In the presentation, the challenges will be outlined and solutions will be proposed. The focus of the discussion will be on SRAM/ROM, but other technologies such as eDRAM and "IT SRAM" will also be addressed.   Platform Leadership in the Ambient Intelligence Era Bob Payne US CTO and Senior Vice President/GM of System ASIC Technology, Philips Semiconductors   Design reuse has become essential to cope with the ever-increasing design complexity. IP level reuse alone has proven insufficient. Platform based design allows the validation of a robust combination of IP blocks and provides a reference HW and SW baseline which can be supported with an integrated development environment. Several years ago we transitioned into the streaming data era with most systems serving as content generation appliances, content consumption appliances or content distribution equipment. Now we have entered the age of ambient intelligence where the streaming data is served up through wireless links. What will platform leadership look like in this new era? How will the SoC infrastructure change as we move to 90nm technology with more than 30M gate per square centimeter integration capacity? How are usage patterns changing and what represents the killer application that enhances the users quality of life by enabling more advanced interaction with the ambient intelligence? What is it going to take to make a step function improvement in system level design productivity? What happens when power optimization becomes the dominant design consideration? What about SoC affordability? What will the SoC design of the future look like? These are just some of the thought provoking issues that will be addressed in Bob Payne’s keynote.          Quality SoC Design and Implementation for Real Manufacturability     Susumu Kohyama Corporate Senior Vice President, Toshiba Corporation   Device miniaturization near 100nm node and beyond together with extreme multi-level interconnect started to create fundamental economical and engineering challenges. Especially, past success model of “Layer Masters” confessed difficulties to fill the gaps between each separated layers to complete integrated results, for meeting performance and yield with a reasonable timing. However, it is also obvious that classic IDM model proved to be so inefficient,  since inevitable separation and standardization of various aspects of design and technology are not established adequately. Those issues are even more significant when we discuss complex SoCs for 90nm and 65nm nodes, where design and implementation commingle in various different manners. A solution for these challenges is a new open idm model where open collaboration and strong differentiator are essential. This presentation will discuss from a “SOC Centric Open IDM” perspective, the whole flow of design and implementation for real manufacturability, where true knowledge of integration and management skill function to enhance differentiators on top of open platforms.       Quality Challenges of the Nanometer Design Realm             Ted Vucurevich Senior Vice President and Chief Technical Office, Cadence Design Systems, Inc.   It is commonly agreed that sub-nanometer design is electronic design technology’s next big challenge. With the economic stakes higher than ever, the vendors of electronic design solutions must put themselves into their customers’ shoes through comprehensive, high-quality programs. My understanding of the differences designers face at geometries below 100 nanometers has led to my discussion of some of the challenges the industry faces in the sub-nanometer realm. This includes the domination of wires in digital design, which requires the ability to design the best quality wires through continuous convergence, a wire-centric methodology. In the nanometer world, the front-end and back-end disappear, leaving the prototype as the chip. This includes detailed wiring, and a new full-chip iteration every day. Most sub-nanometer ICs and SOCs will be digital/mixed-signal. This leads to custom design issues, such as integrating sensitive circuits with massive digital and mixed-signal design, productivity and foundry interface. Nanometer soc verification includes digital, analog and software, and a 70 percent silicon re-spin rate because of associated functional errors. At sub-nanometer levels, design-in becomes a major bottleneck, especially across a design chain, which can only be solved by silicon-package-board co-design.                Addressing the IC Designer’s Needs: Integrated Design Software for Faster, More Economical Chip Design     Rajeev Madhavan Chairman & CEO, Magma Design Automation     Electronic design automation continues to attract a great deal of investment from the venture community, fostering the creation of startup companies focused on developing unique point-tool solutions. While many innovative new technologies come from this, industry must consider the increasingly critical need of ic designers and manufacturers: integrated design flows that enable the design and production of chips with fewer resources and in less time, without compromising the quality of results. Increasingly evident is the advantage of integrated design and the economies it brings while delivering the same quality of results as point-tool-based approaches.  The future of eda depends on the industry’s ability to deliver solutions that enable the ic industry’s integration of electronic design tools and processes as it relies on eda to provide the means for producing the next generation of semiconductor products.     Closing the Gap Between ASIC and Full Custom: A Path to Quality Design   Michael Reinhardt President & CEO, RubiCad Corporation Although process technology has shrunk down to nanometer features over the last decade, the gap between ASIC design and full-custom ic design has widened. This gap includes significant differences in performance, price, and profit between the two design styles. It is also revealed by huge differences in quality between the two styles in speed, power distribution and consumption, yield, and reliability, in some cases as much as an order of magnitude. To fully utilize the latest process technologies, a full-custom design approach with the productivity of an ASIC flow is necessary. Michael Reinhardt will start with an analysis of how the gap between ASIC and full-custom design began, and discuss its long-term consequences on the whole industry. He will then show the positive effects on the quality of IC design, and on the chip industry’s economic situation, which can occur if this gap can be closed. He will illustrate possible strategies and solutions for achieving this closure, and how they can be implemented right now in practical ways.   A VLSI System Perspective for  Microprocessors Beyond 90nm   Shekhar Borkar Fellow & Director of Circuit Research lab, Intel Corporation Microprocessor performance increased by five orders of magnitude in the last three decades. This was made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue to fulfill the microprocessor performance demand; however, with some adverse effects posing barriers—limited by power delivery and dissipation—and not by manufacturing or cost. Therefore, performance at any cost will not be an option; significant improvements in efficiency of transistor utilization will be necessary. This talk will discuss potential solutions in all disciplines, such as microarchitecture, circuits, design technologies & methodologies, thermals, and power delivery, to overcome these barriers for microprocessors beyond 90nm.

 

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ISQED'05  PROGRAM