Welcome to the home page for Icarus Verilog. This is the source for your favorite free implementation of Verilog!

Quick Links:

What is Icarus Verilog?

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.

The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2001. The standard proper was released towards the middle of the year 2001, though in a rather pricey electronic form. This is a fairly large and complex standard, so it will take some time for it to get there, but that's the goal.

Icarus Verilog is a work in progress, and since the language standard is not standing still either, it probably always will be. That is as it should be. However, I will make stable releases from time to time, and will endeavor to not retract any features that appear in these stable releases. The quick links above will show the current stable release.

The main porting target is Linux, although it works well on many similar operating systems. Various people have contributed precompiled binaries of stable releases for a variety of targets. These releases are ported by volunteers, so what binaries are available depends on who takes the time to do the packaging. Icarus Verilog has been ported to That Other Operating System, as a command line tool, and there are installers for users without compilers. You can compile it entirely with free tools, too, although there are precompiled binaries of stable releases. Incidentally, I know for certain that it is 64bit clean, because it is developed on Linux/alpha.

Where is Icarus Verilog?

The Current release is available in source and a variety of binary forms in the FTP directory <ftp://icarus.com/pub/eda/verilog/v0.8/ >. Updates to the stable release may be made from time to time to fix problems, but there should be no compatibility issues within this version. This will continue to be maintained until rendered obsolete by a new stable release.

Development snapshots are made almost weekly, and made available in the FTP directory <ftp://icarus.com/pub/eda/verilog/snapshots >. The files are gzip compressed tar files that contain the source and makefiles. These snapshots follow development progress, and, although the latest features are included in this source, compatibility from snapshot to snapshot is not guaranteed.

And finally, a daily snapshot of my CVS repository is available via anonymous cvs. This allows those who wish to track my progress and contribute with patches timely access to the most bleeding edge copy of the source. Access the verilog source with the commands:

cvs -d :pserver:cvs@icarus.com:/home/demon/anoncvs login

       (Password is "cvs")

cvs -d :pserver:cvs@icarus.com:/home/demon/anoncvs get verilog

From here, you can use normal CVS commmands to update your source to the very latest copy of the source. Note that if you submit patches, it is most convenient for me if they are relative the latest cvs copy of the source. The main trunk of the project is the active development path. If you want to instead access the v0.6 branch, it is tagged v0_6-branch.

When you are working from the CVS version, be aware that the configure scripts are not part of CVS and are instead generated from the configure.in files. There is a small script in the root directory that you can run to make (or update) your configure scripts after a cvs update:

        sh autoconf.sh

This little script runs the autoconf command on the various configure.in files to make your configure scripts. This is how I make the configure scripts when I generate a release or a snapshot.

A Test Suite?

There is also a test suite available, that is being managed by Steve Wilson. The test suite snapshots are here: <ftp://icarus.com/pub/eda/verilog/tests >. The test plan, which is here, describes the purpose of the test suite, and the status of the various tests. Steve has been accepting contributions as well as writing many of the tests himself. Test suite entries are also scraped from bug reports. This is in fact the most common source for test suite programs.

The test suite is also accessible as the ivtest SourceForget.net project, available here: <http://sourceforge.net/projects/ivtest >. The SourceForge version is most interesting as it makes the testsuite available via CVS. Since the test suite is simply an ongoing accumulation of tests, there are not typically any releases, per se.

Who is Icarus Verilog?

The main compiler is written by (and copyright) Stephen Williams. That's me. In fact, I'm still working on it, and will continue to work on it for the forseeable future. I'm a software engineer specializing in device drivers and embedded systems, although I have some limited hardware design experience. Even so, I am a software engineer writing software for hardware designers, so expect the occasional communications glitch:-)

There is also a cast of characters who have contributed patches, tests, and various bits to the project. I'll be adding a credits page as soon as I catch my breath, although the source distributions do in general name names.

There is currently no mailing list unique to Icarus Verilog , but it is often discussed in the gEDA-dev mailing list. See the gEDA home page for information about that project, and information about how to join the mailing list. While you are browsing the gEDA web site, notice all the other nifty EDA related tools that are there. While Icarus Verilog is not literally part of the gEDA project, we cooperate and try to support each other. Icarus Verilog users are often gEDA users as well.

Technical Support

Support for Icarus Verilog is self serve. The software distribution includes documentation (as ASCII text) that is the first place to start for help. I include here a FAQ page that attempts to answer some questions about the software and its use. If the documentation and the FAQ fail you, then Icarus Verilog is discussed on the gEDA-dev mailing list. I and other contributers read the list regularly, and I encourage users to subscribe to the list, so in that forum you have a chance of getting a human being to help you.

If you think you have found a bug, then see the "Bugs " page. This tells you how and where to report bugs with the software. I try to promptly look to bug reports, but this is free software that I work on when (if!) I have time so please don't get impatient.

Resources, Etc.

For learning Verilog, it's hard to beat "Verilog Quickstart" by James Lee. It does a good job of explaining the proper use of Verilog, without being condescending. And besides that, this is a real, physical, book that you can open and read on the train without draining laptop batteries. Everyone at my day job has a copy, some have two. Get yours at www.jmlzone.com.

The C programmers amongst you may be interested in the VPI interface to Verilog, and the book on that subject is "The Verilog PLI Handbook " by Stuart Sutherland. I refer to it often. Sutherland HDL can be found at www.sutherland-hdl.com, and the book can be purchased directly.

Tons of open source EDA resources, as well as news on open source EDA development, can be found at the Open Collector web site. It's interesting browsing.

Linux Journal printed a feature article about Icarus Verilog in their February 2001 issue. For the first year it was available in print only, but now the article is now available on line at <http://www.linuxjournal.com/article.php?sid=4428 >. The July 2002 issue includes two articles about Icarus Verilog, one of which is available here <http://www.linuxjournal.com/article.php?sid=6001 >.

The Icarus image seen as the background, and as the logo for Icarus Verilog, was contributed by Charles F. Wilson in order to represent Icarus Verilog.

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