LEON3 Processor IntroductionThe LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing to be used in any commercial application.The LEON3 processor has the following features:
The LEON3 processor is distributed as part of the GRLIB IP library, allowing simple integration into complex SOC designs. GRLIB also includes a configurable LEON3 multi-processor design, with up to 4 CPU's and a large range of on-chip peripheral blocks. SynthesisThe LEON3 processor can be synthesised with the most common synthesis tools such as Synplify, Synopsys DC and Cadence RC. The core will reach up 125 MHz on FPGA and 400 MHz on 0.13 um ASIC technologies. The core area (pipeline, cache controllers and mul/div units) requires only 20 - 25 Kgates or 3500 LUT, depending on the configuration.SoftwareA Bare-C cross-compiler for LEON3 is available from the download pages, as well as an RTEMS cross-compiler based on the latest stable RTEMS release (4.6.1). A port of Snapgear Linux is also availble, while a port of eCos is in progress.* SPARC is a registered trademark of SPARC International. | ||