• SPARC V8 compliant integer unit with 5-stage pipeline
  
• Hardware multiply, divide and MAC units
  
• Interface to the Meiko FPU and custom co-processors
  
• Separate instruction and data cache (Hardvard architecture)
  
• Set-associative caches: 1 - 4 sets, 1 - 64 kbytes/set. Random, LRR or LRU replacement
  
• Data cache snooping
  
• AMBA-2.0 AHB and APB on-chip buses
  
• 8/16/32-bits memory controller for external PROM and SRAM
  
• 32-bits PC133 SDRAM controller
  
• On-chip peripherals such as uarts, timers, interrupt controller and 16-bit I/O port
  
• Advanced on-chip debug support unit and trace buffer
  
• Power-down mode
  

• On-chip 0-waitstate scratch pad data RAM
  
• Interface to high-performance IEEE-754 FPU (GRFPU/GRFPC)
  
• Low complexity 32-bit PCI target-only interface
  
• 10/100 Ethernet MAC (based on the Opencores MAC core)
  
• SPARC V8 Reference Memory management unit (SRMMU)
  
• Also synthesizable with Xilinx XST synthesis tool
  
• lncludes synthesis and P&R scripts for several fpga boards
• Supports Cadence NCSIM and GNU GHDL simulators
  

Synthesis

The VHDL model is fully synthesisable and contains synthesis scripts for Synopsys FPGA-Compiler, Synopsys-DC,  Synplify and Xilinx XST (-xst version of leon only). Targeting a 0.25 um CMOS process (std-cell), more than 125 MHz can be reached with a gate count of less than 30 Kgates. The processor also fits in an Altera 10K200E FPGA or Xilinx XCV300. Synthesis is straight-forward thanks to the robust design style: fully synchronous, single clock, no false paths, all inputs and outputs are latched. A paper describing the coding style used in LEON can be found here.

The following synthesis results have been achieved:

Technology	Area	Timing
Atmel 0.18 CMOS std-cell	35K gates + RAM	165 MHz (pre-layout)
Atmel 0.25 CMOS std-cell	33K gates + RAM	140 MHz (pre-layout, log file)
UMC 0.25 CMOS std-cell	35K gates + RAM	130 MHz (pre-layout)
Atmel 0.35 CMOS std-cell	2 mm2 + RAM	65 MHz (pre-layout, log file)
Xilinx XC2V3000-6	5,000 LUT + block RAM	80 MHz (post-layout, log1, log2)
Altera 20K200C-7	5,700 LCELLs + EAB RAM	49 MHz (post-layout) log file
Actel AX1000-3	7,600 cells + RAM	48 MHz (post-layout) log file

The area in the table reflects the complete processor with on-chip peripherals and memory controller. The area of the processor core only (IU + cache controllers) is about half of that. The timing for the ASIC technologies has been obtained using worst-case process corner and industrial temperature range.

Configuration

The VHDL model can now be configured using a graphical tool built on tkconfig from the linux kernel. This allows new users to quickly define a suitable custom configuration. Below is a snapshot of the tool under linux (click on image for larger view):



SPARC V8 compliance

The LEON2 processor has been formally certified by SPARC international as being SPARC V8 compliant. The certification was achived on April 2, 2003, and was co-sponsored by ESA and Silicon and Software Systems.

Embedded software

Being SPARC V8 compliant, compilers and kernels for SPARC V8 can be used with LEON (kernels will need a LEON bsp). To simplify initial software development, Gaisler Research is providing LECCS, a free C/C++ cross-compiler system based on gcc and the RTEMS real-time kernel. LECCS allows cross-compilation of single or multi-treaded C and C++ applications for both LEON and ERC32. Using the gdb debugger, it is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Gaisler Research also provides TSIM, a high-performance LEON simulator which seamlessly can be attached to gdb and emulate a LEON system at more than 10 MIPS.

A LEON (and ERC32) port to the eCos real-time kernel has been made, and is included in the current eCos v2.0 CVS repository. The binaries are compatible with TSIM, mkprom, rdbmon and DSUMON. No support for a hardware FPU is currently provided, but emulated FP operations using -msoft-float works fine. The LEON target package is called leon, you should thus use ecosconfig new leon to create a leon configuration. For further information on eCos, see the eCos documentation page.

Those interested in JAVA on LEON can take a look at the UCLA Thumbod project. Thumbpod is based on LEON and uses KVM from Sun to execute the java-based application software.

LINUX support for LEON is provided through a special version of the SnapGear Embedded Linux distribution. SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. The LEON port of SnapGear supports both MMU and non-MMU LEON configurations, as well as the optional V8 mul/div instructions and floating-point unit (FPU). A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.

On-chip Debug support unit

The advanced Debug Support Unit (DSU) in LEON2 allows non-intrusive debugging and tracing of applications running on LEON target hardware. The DSU can insert both breakpoints and data watchpoints, and provides full access to all on-chip registers and buses. A trace buffer makes it possible to trace executed instructions, AHB bus transfers, or both. The DSU communicates with an outside monitor through a dedicated uart, and does not need any (expensive) special hardware. Gaisler Research provides the multi-platform monitor GRMON that supports both stand-alone debugging as well as an interface to the GDB debugger.

Performance

Using the Dhrystone 2.1 benchmark, LEON executes around 1,500 dhrystones/s/MHz. This translates to roughly 0.85 dhrystone MIPS/MHz. Configurations with hardware mul/div and larger caches usually performs somewhat better. The dhrystone benchmark was compiled with LECCS-1.1.5 (gcc-2.95.3) using -O2 optimisation.

Sample LEON implementations

Below are a few LEON ASIC implementations made by various companies and research institutions. Click on the links for further details.

LEON1FT (ATC35, Atmel)	LEON2FT (UMC 0.18, IMEC/ESA)	LEON2 (TSMCS 0.25, A-Star)	LEON2-based NJ1030 GPS baseband receiver by Nemerix (CH)

A rad-hard LEON2-FT implementation is being developed by Atmel under ESA contract.

A family of LEON2 based devices for consumer and military  applications is availble from Orbita.

NEW: a list of research projects using LEON is available here.

LEON Development boards

Gaisler Research and Pender Electronic Design have developed a low-cost FPGA prototyping board suitable for LEON development. The board includes a Virtex-II XC2V3000 FPGA, 8 Mbyte flash prom, 1 Mbyte SRAM and 64 Mbyte PC133 SDRAM. The board has a PCI form factor and can be used stand-alone as well as inserted in a legacy PC. Two 120-pin connectors are provided for custom expansion. Boards with larger FPGAs as well as LEON ASIC implementations are also available. For more information, see the boards page.



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