GRLIB IP Library
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
The library includes cores for AMBA AHB/APB control, the LEON3 SPARC processor, 32-bit PC133 SDRAM controller, 32-bit PCI bridge with DMA, 10/100 Mbit ethernet MAC, 8/16/32-bit prom and sram controller, CAN controller, UART with FIFO, modular timer unit, interrupt controller, and a 32-bit GPIO port. Memory and pad generators are available for Virage, Xilinx, UMC, Atmel, and Actel.
The library is provided undet the GNU GPL license, but can also be provided under commercial licensing conditions. Contact Gaisler Research if you want to use GRLIB in a commercial product.
Documentation and downloadsGRLIB product brief
GRLIB online documentation v0.15 (also included in the source code below)
GRLIB VHDL source code: grlib-beta-0.15.tar.gz
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