HomeNewsletterAboutFeedbackContact UsMedia KitEET Network


NetSeminar Button



NeSeminar Services
A list of upcoming NetSeminars, plus a link to the archive.

• EE Times' Future of Semiconductors NetSeminar Series

• RapidIO and QNX Neutrino RTOS - A Seamless Fit

Archive


EETimes Design Library

International Job Search
eLibrary


Online Editions
EE TIMES
EE TIMES ASIA
EE TIMES CHINA
EE TIMES FRANCE
EE TIMES GERMANY
EE TIMES KOREA
EE TIMES TAIWAN
EE TIMES UK

Web Sites
CommsDesign
iApplianceWeb.com
Microwave Engineering
EEdesign
Deepchip.com
Design & Reuse
Embedded.com
Embedded Edge
   Magazine
Elektronik i Norden
Planet Analog
Silicon Strategies
The Work Circuit
Wireless Solutions
   Magazine


Conferences and Events
Custom Magazines
EBN
EBN China
eeProductCenter
Electronics Express
NetSeminar Services
QuestLink




Advertisement

Looking for a breakthrough in analog, & mixed-signal design simulation? Then look at Nassda's HSIM with new digital co-simulation.To learn more, click here. .


February 2, 2004


IC placement benchmarks needed, researchers say

By Richard Goering
EE Times

April 10, 2003 (10:36 AM EDT)
 
Latest Headlines
News
Roving eye for Mars forces CCD rethink
Layout, synthesis sales boost Magma results
EDA startup 'views' OpenAccess database
Cadence hits revenue target but not bookings expectations
Synopsys acquires ADA for analog boost
Synopsys buys Analog Design Automation
Mentor Q4 suggests selective EDA recovery

Archives

MONTEREY, Calif. — Following up on a controversial study that claimed IC placement algorithms are severely deficient, researchers at the International Symposium on Physical Design (ISPD) here Tuesday (April 8) struggled to find a benchmarking methodology for IC physical design. A diverse, publicly-available benchmark suite is needed before solid conclusions can be made, one presenter said.

In a paper presented at the ASP-DAC conference in Japan early this year, UCLA researchers led by Jason Cong, co-director of the VLSI CAD lab at UCLA, evaluated several academic placers along with Cadence Design Systems' QPlace. They concluded that IC placement algorithms leave so much excess wire length that chip designs are essentially several technology generations behind where they should be.

What was perhaps most controversial about the paper was its use of synthetic benchmarks in which optimal wire lengths are known. EDA vendors noted that the benchmarks may not be representative of real-world circuits, and they said that criteria such as routability, timing and signal integrity are more important than wire length.

At ISPD, Cong co-authored a follow-up paper that evaluated both partitioning and placement algorithms. Presented by UCLA student Min Xie, it looked only at the academic placers Dragon, Capo and mPL. Xie said that the previous paper's inclusion of QPlace "raised a lot of eyebrows," and that the researchers felt they'd be better off with academic placers for which they had source code.

The paper concluded that partitioning algorithms perform very well on a bi-partitioning example with known upper bounds (BEKU) suite, but not so well on a multi-way partitioning example with known upper bounds (MEKU) suite. The placement algorithms were evaluated using UCLA's placement examples with known upper bounds (PEKO) suite. Xie acknowledged a serious flaw in the PEKO suite—all nets are local, and there are no global wires, as there would be in real circuits.

Xie said researchers found that the academic placement algorithms, which underlie many commercial tools, diverge from optimal wire-length solutions by 1.46 to 2.38 times. Then they looked at benchmark suites that included global nets. Results weren't good here either, and they differed from the PEKO suite. For example, mPL gave the best results without global nets, but its quality ratio declined by 80 percent in the presence of a few non-local nets.

"None of these placement algorithms perform universally well under different scenarios," said Xie. "We think it's another validation that much needs to be done for the reduction of wire length in placement."

Another presenter was more hesitant to make sweeping conclusions about placement algorithms. Igor Markov, assistant professor at the University of Michigan, said that a truly representative, and public, benchmark suite is what's needed now.

Markov discussed the many requirements faced by placement tools, including the need to manage large amounts of empty "white" space on fixed-die ICs. "With so many requirements and constraints, we have to worry about benchmarking," he said. "We need to understand how algorithms work over a wide set of examples. It's important for the industry to embrace open benchmarking."

Markov reviewed a number of open benchmark suites, and discussed their limitations, such as PEKO's avoidance of global wires. He showed that a placement algorithm that scores well on one benchmark suite might fare very poorly on another. For example, Dragon does well on the IBM benchmarks that come with it, but not others.

"We need real benchmarks not provided by the authors of any of these papers, including myself," Markov said. Markov is the co-author of the Capo placer.

Further, there's more to consider that wire length. Markov noted that there's no common metric for routability, and no good public benchmarks for routing. But the toughest part of benchmarking, he said, is timing-driven placement. The "quality of results" metrics are not clearly defined, he noted.

A significant point about Markov's paper is the collaboration behind it. In addition to the University of Michigan, it has co-authors from Binghamton University, IBM and Monterey Design Systems. It also acknowledges assistance from other researchers, including Jason Cong.

Free Subscription to EE Times
First Name Last Name
Company Name Title
Business Address City
State

 Zip
Email address 

eeProductCenter is here!
Looking for the very latest IC or component? eeProductCenter, from the editors of EETimes and ChipCenter, reports on new products in 15 major technology categories such as: Analog ICs, Boards/Buses, DSPs, Embedded Tools, Interconnects, Memory, Microprocessors, Passives/Sensors, PLDs/FPGAs, Power, RF/Microwave, Test & Measurement, etc. Read it here first, so you can build it fast.
Silicon Strategies Adds New Features
Since 1997, Silicon Strategies has been the leading 24/7 news site for the semiconductor industry, focused on breaking the latest news and delivering expert analysis and commentary on major events for semiconductor professionals. Recently we've added a number of new weekly features on foundries, DRAM analysis, a weekly recap and a daily email newsletter. Click here for more.
An Industry Agenda
"The future ain't what it used to be," Yogi Berra once quipped. He could have been referring to today's semiconductor industry, writes editorial director Richard Wallace in "The Future of Semiconductors." In this special issue, the editors of EE Times create a blueprint for the industry with their analysis of key technology, business and geopolitical realities. Register for the related Editorial NetSeminar series which begins later this month.

• Prototype Circuit Boards from PCBexpress
Two-layer, 20-piece at $11 each, ship in 24-hours. Four-layer, 10-piece at $19 each, ship in 48 hours. No tooling charges for our quality prototype boards. No hassles, easy order process.

• PCB123-the FREE PCB Solution, Design to Order
Remove engineering bottle-necks with our FREE and easy to use schematic and layout software. Quotes your boards as you design! Quick and easy solution for up to 4-layer circuit board designs.

• Techniques to Future-Proof Embedded CPU Designs
Engineers must design for the future. Feature creep, software bloat, shifting standards, and competition require a design with legs. View this free webinar to examine performance, cost, power, heat, layout, components and firmware for scalability.

• *~Free Technical Publications~*
New papers available in the following design categories: IC Design & Verification, FPGA Design, Functional Verification, Design for Test and PCB Design. To select a category, CLICK HERE!

• The Fastest Embedded Processor Ever - Xtensa V
Test drive Tensilica's Xtensa V embedded 32-bit processor, the fastest ever according to EEMBC Certification Labs.

Buy a link NOW:

Home  |  Register  |  About  |  Feedback  |  Contact
Copyright © 2004 CMP Media, LLC
Terms and Conditions  |  Privacy Statement