Igor Markov's publications (author lists in older papers are alphabetized)

Several publications referenced by DBLP.

Also try

1. In Books
2. Journal papers
3. Publications in Conference and Workshop Proceedings
4. Invited talks
5. Conference and Workshop Presentations w/o Proceedings
6. Abstracts and Technical Reports

• A. Ramani and I. L. Markov, ``Automatically Exploiting Symmetries in Constraint Programming'', (.pdf) Lecture Notes in Computer Science vol. 3419, p. 98, Springer, March 2005.
• D. B. Motter and I. L. Markov, ``A Compressed Breadth-First Search For Satisfiability'', (.ps), (.pdf) In Lecture Notes in Computer Science vol. 2409, Springer, 2002, pp. 29-42.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, ``Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning'', (.ps), (.pdf) In Lecture Notes in Computer Science vol. 1619, Springer, 1999, pp. 177-193.

  Papers in journals and magazines

  • F. A. Aloul, K. A. Sakallah, and I. L. Markov, ``Efficient Symmetry Breaking for Boolean Satisfiability'', to appear in IEEE Trans. on Computers, 2006.
  • K. M. Svore, A. W. Cross, I. L. Chuang, A. V.Aho and I. L. Markov, ``A Layered Software Architecture for Quantum Computing Design Tools'', to appear in IEEE Computer, 2006.
  • S. N. Adya, I. L. Markov and P. G. Villarrubia, ``On Whitespace and Stability in Min-cut Placement'', (.pdf), to appear in Integration: the VLSI Journal, 2006.
  • J. A. Roy, S. N. Adya, D. A. Papa and I. L. Markov, ``Min-cut Floorplacement'', (.pdf), to appear in IEEE Trans. on Computer-Aided Design, 2006.
  • V. V. Shende, S. S. Bullock, I. L. Markov, ``Synthesis of Quantum Logic Circuits'' (.pdf), to appear in IEEE Trans. on Computer-Aided Design, May 2006.

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  • G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Is Quantum Search Practical?'' (.pdf), IEEE/AIP Computing in Science and Engineering, May/June 2005, pp. 62-70.
  • A. Ramani, F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Breaking Instance-Independent Symmetries in Exact Graph Coloring'' (.pdf), to appear in Journal of Artificial Intelligence Research, 2005.
  • D. B. Motter, J. A. Roy, and I. L. Markov, ``Resolution Cannot Polynomially Simulate Compressed-BFS'' (.pdf), Annals of Mathematics and Artificial Intelligence, vol.44, no.1-2, pp. 121-156, May 2005.
  • G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Graph-based Simulation of Quantum Computation in the Density Matrix Representation'' (.pdf), Quantum Information and Computation, vol.5, no.2 pp. 113-130, February 2005.
  • S. N. Adya and I. L. Markov, ``Combinatorial Techniques for Mixed-size Placement'' (.pdf), ACM Trans. on Design Automation of Electronic Systems, vol. 10, no. 5, January 2005.
  • V. V. Shende and I. L. Markov, ``Quantum Circuits for Incompletely Specified Two-Qubit Operators'' (.pdf), Quantum Information and Computation, vol.5, no.1, pp. 49-57, January 2005.

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  • F. A. Aloul, I. L. Markov and K. A. Sakallah, ``MINCE: A Static Global Variable-Ordering for SAT Search and BDD Manipulation'' (.pdf), Journal of Universal Computer Science, vol. 10, no. 12, pp. 1559-1562, December 2004.
  • K. N. Patel and I. L. Markov, ``Error Correction and Crosstalk Avoidance in DSM Busses'' (.pdf) IEEE Trans. on VLSI vol. 12, no. 10, pp. 1076-1081, October 2004.
  • K. N. Patel, J. P. Hayes, and I. L. Markov, ``Fault Testing for Reversible Circuits'' (.pdf), IEEE Trans. on CAD, 23(8), pp. 1220-1230, August 2004.
  • V. V. Shende, S. S. Bullock, and I. L. Markov, ``Recognizing Small-circuit Structure in Two-qubit Operators,'' (quant-ph/0308045), APS Physical Review A 70, 012310-012314, July 2004. Reprinted in APS/AIP Virtual Journal of Quantum Information, August 2004.
  • V. V. Shende, I. L. Markov, and S. S. Bullock, ``Minimal Universal Two-qubit Controlled-NOT-based Circuits'' (quant-ph/0308033), APS Physical Review A 69, 062321-062329, July 2004. Reprinted in APS/AIP Virtual Journal of Quantum Information, July 2004.
  • S. N. Adya et al., ``Benchmarking for Large-Scale VLSI Placement and Beyond,'' (.pdf) IEEE Trans. on CAD, 23(4), April 2004, pp. 472-488.
  • S. S. Bullock and I. L. Markov, ``Asymptotically Optimal Circuits for Arbitrary n-qubit Diagonal Computations,'' (quant-ph/0303039), Quantum Information and Computation, vol. 4, no. 1, January 2004, pp. 27-47.

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  • S. N. Adya and I. L. Markov, ``Fixed-outline Floorplanning : Enabling Hierarchical Design'' (.pdf), IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135.
  • A. Caldwell, A. B. Kahng and I. L. Markov, ``Hierarchical Whitespace Allocation in Top-down Placement'' (.pdf), IEEE Trans. on CAD, vol. 22(11), November 2003, pp. 716-724.
  • G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Improving Gate-Level Simulation of Quantum Circuits'' (.pdf), (quant-ph/0309060), Quantum Information Processing, vol. 2(5), October 2003, pp. 347-380.
  • F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry'' (.pdf), IEEE Trans. on CAD, vol. 22(9), Sept 2003, pp. 1117-1137.
  • S. S. Bullock and I. L. Markov, ``An Arbitrary Two-qubit Computation in 23 Elementary Gates,'' (.pdf) APS Physical Review A vol. 68(1), July 2003, 012318-012325.
    Reprinted in APS/AIP Virtual Journal of Quantum Information, August 2003.
  • V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Synthesis of Reversible Logic Circuits'' (.pdf), IEEE Trans. on CAD, vol 22(6), June 2003, pp. 710-722 (best paper award).
  • Y. Cao, A. B. Kahng, X. Huang, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, "Improved A Priori Interconnect Predictions and Technology Extrapolation in the GTX System" (.pdf), IEEE Trans. on VLSI, vol. 11(1), January 2003, pp. 3-14.

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  • A. A. Kennings and I. L. Markov, "Smoothening Max-terms and Analytical Minimization of Half-Perimeter Wirelength" (.ps), (.pdf), VLSI Design, vol. 14, no. 3, 2002, pp. 229-237.
  • A. E. Caldwell, A. B. Kahng and I. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms" (.pdf), IEEE Design and Test, May 2002, pp. 72-81.

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  • R. Baldick, A. B. Kahng, A. A. Kennings and I. L. Markov, "Efficient Optimization by Modifying the Objective Function", (.ps), (.pdf), IEEE Trans. on Circuits and Systems, vol. 48, no. 8, pp. 947-957, 2001.
  • A. B. Kahng et al., "Constraint-Based Watermarking Techniques for Design Intellectual Property Protection", (.pdf), IEEE Trans. on CAD, vol. 20, no. 10, 2001, pp. 1236-1252.

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  • A. E. Caldwell, A. B. Kahng, I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout", (.ps), (.pdf), IEEE Trans. on CAD, vol. 19, no. 11, pp. 1304-1314, 2000.
  • A. E. Caldwell, A. B. Kahng, I. L. Markov, "Iterative Partitioning With Varying Node Weights", (.ps), (.pdf) VLSI Design, vol. 11, no. 3, 2000, pp. 249-58
  • C. J. Alpert, A. E. Caldwell, A. B. Kahng, I. L. Markov, "Hypergraph Partitioning With Fixed Vertices", (.ps), (.pdf), IEEE Trans. on CAD, vol. 19, no. 2, 2000, pp. 267-272.
  • A. E. Caldwell, A. B. Kahng, I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning", (.ps), (.pdf) ACM Journal on Experimental Algorithms, vol. 5, 2000.

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  • C. J. Alpert, A. E. Caldwell, T. F. Chan, D. J.-H. Huang, A. B. Kahng, I. L. Markov and M. S. Moroz, "Analytic Engines Are Unnecessary in Top-Down Partitioning-Based Placement" (.ps), VLSI Design, 10(1) (1999), pp. 99-116.
  • A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky,   "On Wirelength Estimations for Row-Based Placement",  (.ps), (.pdf), IEEE Trans. on CAD 18(9), (1999), pp. 1265-1278.

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• C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement" (.ps), (.pdf), IEEE Trans. on CAD 17(1) (1998), pp. 3-13.

Publications In Conference and Workshop Refereed Proceedings

• J. A. Roy, J. F. Lu and I. L. Markov, ``Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement'', to appear in Proc. Int'l Symp. on Physical Design (ISPD), San Jose, CA, April 2006.
• A. N. Ng, R. Aggarwal, V. Ramachandran, I. L. Markov ``Solving Hard Instances of Floorplacement'' to appear in Proc. Int'l Symp. on Physical Design (ISPD), San Jose, CA, April 2006.
• D. A. Papa and I. L. Markov, ``Utility of OpenAccess in Academic Research'' (.pdf), to appear in Proc. Asia and South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan, January 2006.

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• K.-H. Chang, I. L. Markov and V. Bertacco, ``Post-Placement Rewiring and Rebuffering by Exhaustive Search For Functional Symmetries'' (.pdf), Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 56-63, San Jose, CA, November 2005.
• K.-H. Chang, V. Bertacco and I. L. Markov, ``Simulation-based Bug Trace Minimization with BMC-based Refinement'', (.pdf), Proc. Int'l Conf. Computer-Aided Design (ICCAD), pp. 1045-1051, San Jose, CA, November 2005.
• S. Krishnaswamy, I. L. Markov and J. P. Hayes, ``Testing Logic Circuits for Transient Faults'' (.pdf), in Proc. IEEE Eur. Test Symp. (ETS), pp. 102-107, Tallin, Estonia, May 2005.
• J. A. Roy, D. A. Papa, S. N. Adya, H. H. Chan, J. F. Lu, A. N. Ng, I. L. Markov, ``Capo: Robust and Scalable Open-Source Min-cut Floorplacer'' (.pdf), Proc. Intl. Symposium on Physical Design (ISPD), pp. 224-227, San Francisco, April 2005.
• Zh. Xiu, D. A. Papa, P. Chong, A. Kuehlmann, Rob A. Rutenbar, Igor L. Markov, ``Early Research Experience with OpenAccess Gear: An Open Source Development Environment for Physical Design'' (.pdf), Proc. Intl. Symposium on Physical Design (ISPD),A pp. 94-100, San Francisco, April 2005.
• H. H. Chan, S. N. Adya and I. L. Markov, ``Are Floorplan Representations Useful in Digital Design?'', (.pdf), Proc. Intl. Symposium on Physical Design (ISPD), pp.129-136, San Francisco, April 2005.
• A. N. Ng and I. L. Markov, ``Toward High Quality Tools and Tool Flows Through High-Performance Computing'', (.pdf), Proc. Intl. Symp. on Quality Electronic Design (ISQED), pp. 22-27, San Jose, California, March 2005.
• S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Accurate Reliablity Evaluation and Enhancement via Probabilistic Transfer Matrices'', (.pdf), Proc. Design Automation and Test in Europe (DATE), pp. 282-287, Munich, Germany, March 2005 (best paper award).
• I. L. Markov and D. Maslov, ``Uniformly-switching Logic for Cryptographic Applications'' (.pdf), Proc. Design Automation and Test in Europe (DATE), Munich, Germany, pp. 432-433, March 2005.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Dynamic Symmetry-Breaking for Improved Boolean Optimization'', Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC) (.pdf), pp. 445-450, Shanghai, China, January 2005.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Synthesis of Quantum Logic Circuits'', Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC) (.pdf), pp. 272-275, Shanghai, China, January 2005.

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• S. N. Adya, S. Chaturvedi, J. A. Roy, D. A. Papa and I. L. Markov, ``Unification of Partitioning, Floorplanning and Placement'' (.pdf, slides), Intl. Conf. Computer-Aided Design (ICCAD), San Jose, CA, November 2004, pp. 550-557.
• P. T. Darga, M. H. Liffiton, K. A. Sakallah and I. L. Markov, ``Exploiting Structure in Symmetry Generation for CNF'' (.pdf), Proc. Design Autom. Conf. (DAC), San Diego, California, June 2004, pp. 530-534.
• Y. Oh, M. Mneimneh, Z. S. Andraus, K. A. Sakallah and I. L. Markov, ``AMUSE: A Minimally Unsatisfiable Subformula Extractor'' (.pdf), Proc. Design Autom. Conf. (DAC),(BPA nominee) San Diego, California, June 2004, pp. 518-523.
• A. B. Kahng, I. L. Markov and S. Reda, ``On Legalization of RowBased Placements'' (.pdf), Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 214-219.
• H. H. Chan and I. L. Markov, ``Practical Slicing and Nonslicing Block-Packing without Simulated Annealing'' (.pdf), Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 282-287.
• D. A. Papa, S. N. Adya and I. L. Markov, ``Constructive Benchmarking for Placement'' (.pdf), Proc. Great Lakes Symp. on VLSI (GLSVLSI), Boston, Massachusetts, April 2004, pp. 113-118.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Finding Small Two-qubit Circuits'' (.pdf), Proc. SPIE vol. 5436 (Conf. on Quantum Information and Computation), pp. 348-359, Orlando, Florida, April 2004.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Graph-based Simulation of Quantum Computation in the State-vector and Density-matrix Representation,'' (.pdf), Proc. SPIE vol. 5436 (Conf. on Quantum Information and Computation), pp. 285-296. Orlando, Florida, April 2004.
• A. Ramani, F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Breaking Instance-Independent Symmetries in Exact Graph Coloring'' (.pdf), Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 324-329.
• V. V. Shende, I. L. Markov and S. S. Bullock, ``Smaller Two-Qubit Circuits for Quantum Communication and Computation'' (.pdf), Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 980-985.
• A. B. Kahng, I. L. Markov and S. Reda, ``Boosting: Min-Cut Placement with Improved Signal Delay'' (.pdf), Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 1098-1103.
• G. F. Viamontes, I. L. Markov and J. P. Hayes, ``High-performance QuIDD-based Simulation of Quantum Circuits,'' (.pdf), Proc. Design Autom. and Test in Europe (DATE), Paris, France, February 2004, pp. 1354-1359.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Symmetry-Breaking for Pseudo-Boolean Formulas'' (.pdf), Proc. Asia and South Pacific Design Autom. Conf. (ASPDAC), Yokohama, Japan, January 2004, pp. 884 - 887.

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• S. N. Adya, I. L. Markov and P. G. Villarrubia, ``On Whitespace and Stability in Mixed-Size Placement,'' in Proc. Intl. Conf. on Computer-Aided Design(ICCAD) (.pdf), San Jose, November 2003, pp. 311-318.
• F. A. Aloul, I. L. Markov, and K. A. Sakallah, ``Efficient Symmetry Breaking for Boolean Satisfiability,'' (.pdf) in Proc. Intl. Joint Conf. on Artificial Intelligence (IJCAI), pp. 271-282, Acapulco, Mexico, August 2003.
• A. Ramani and I. L. Markov, ``Combining Two Local Search Approaches to Hypergraph Partitioning,'' (.pdf) Proc. Intl. Joint Conf. on Artificial Intelligence (IJCAI), pp. 1546 - 1548, Acapulco, Mexico, August 2003.
• S. Bullock and I. L. Markov, ``An Arbitrary Two-qubit Computation In 23 Elementary Gates Or Less,'' (.pdf) (.ppt) Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 324-329, Anaheim, CA, June 2003 (BPA nominee).
• F. A. Aloul, K. A. Sakallah, and I. L. Markov, ``Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability'', (.pdf) (.ppt) Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 836-839, Anaheim, CA, June 2003.
• K. N. Patel, J. P. Hayes and I. L. Markov, ``Fault Testing for Reversible Circuits,'' (.pdf) Proc. IEEE VLSI Test Symposium (VTS), pp. 410-416, Napa, CA, April 2003.
• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``FORCE: A Fast and Easy-To-Implement Variable-Ordering Heuristic,'' (.pdf), Proc. Great Lakes Symp. on VLSI (GLSVLSI), pp. 116-119, Washington, DC, 2003.
• S. N. Adya, M. Yildiz, I. L. Markov, P. G. Villarrubia, P. N. Parakh and P. H. Madden, ``Benchmarking For Large-Scale Placement and Beyond'', (.pdf), (.ppt), Proc. Intl. Symp. on Physical Design (ISPD), pp. 95-103, Monterey, CA, April 2003.
• K. N. Patel and I. L. Markov, ``Error-Correction and Crosstalk Avoidance in DSM Busses,'' Proc. Intl. Workshop on System-Level Interconnect Prediction (SLIP) (.pdf) pp. 9-14, Monterey, CA, April 2003.
• A. B. Kahng and I. L. Markov, ``The Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint'', in Proc. Intl. Symp. on Quality Electronic Design (ISQED), pp. 208-213, San Jose, CA, March, 2003.
• S. N. Adya and I. L. Markov, ``Improving Min-cut Placement for VLSI Using Analytical Techniques,'' in Proc. IBM ACAS Conference, pp. 55-62, Austin, TX, February, 2003.
• G. F. Viamontes, M. Rajagopalan, I. L. Markov and J. P. Hayes, ``Gate-level Simulation of Quantum Circuits'', (.pdf) Proc. Asia and South-Pacific Design Automation Conf. (ASPDAC), pp. 295-301, Kitakyushu, Japan, January 2003.

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• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Generic ILP versus Specialized 0-1 ILP: an Update'', (.pdf) in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design (ICCAD), pp. 450-457, November 2002.
• V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Reversible Logic Circuit Synthesis'', (.ps, .pdf) in Proc. ACM/IEEE Intl. Conf. Comp.-Aided Design (ICCAD), pp. 353-360, November 2002.
• F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Improving the Efficiency of Circuit-to-BDD Conversion by Gate and Input Ordering'' (.pdf), in Proc. ACM/IEEE Intl. Conf. Computer Design (ICCD), pp. 64-69, September 2002, Freiburg, Germany.
• G. F. Viamontes, M. Rajagopolan, I. L. Markov and J. P. Hayes, ``High-Performance Simulation of Quantum Computation Using QuIDDs'' (.pdf), Proc. Quantum Communication, Measurement and Computation (QCMC) June 2002, pp. 311-314.
• F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult SAT Instances In The Presence of Symmetry'' (.ps) (.pdf), slides: .ppt, .pdf, in Proc. ACM/IEEE Design Automation Conf. (DAC), pp. 731-736, June 2002.
• S. N. Adya and I. L. Markov, ``Consistent Placement of Macro-blocks Using Floorplanning and Standard-Cell Placement'', (.ps) (.pdf), in Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), pp. 12-17, April 2002.
• A. B. Kahng, S. Mantik and I. L. Markov, ``Min-max Placement For Large-scale Timing Optimization'' (.ps) (.pdf), in Proc. ACM/IEEE Intl. Symp. on Physical Design (ISPD), pp. 143-148, April 2002.
• A. B. Kahng and I. L. Markov, ``Analytical Minimization of Signal Delays in VLSI Placement'', (.ps) (.pdf), Proc. 3rd Annual IBM ACAS Conference, pp. 62-68, February, 2002.

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• F. A. Aloul, I. L. Markov and K. A. Sakallah ``Faster SAT and Smaller BDDs via Common Function Structure'' (.pdf), slides: (.ppt), (.pdf), in Proc. ACM/IEEE Intl. Conf. Computer-Aided Design, pp. 443-448, 2001.
• S. N. Adya and I. L. Markov, ``Fixed-outline Floorplanning Through Better Local Search'', (.ps), (.pdf) slides: (.ppt), (.pdf), in Proc. ACM/IEEE Intl. Conf. Computer Design, pp. 328-334, 2001.

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• A. E. Caldwell, Y Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, "GTX: The MARCO GSRC Technology Extrapolation System", (.ps), (.pdf), slides(.ppt), (.ps), (.pdf), in Proc. ACM/IEEE Design Automation Conf., Los Angeles, June 2000, pp. 693-698.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?", (.ps), (.pdf), slides(.ppt), (.ps), (.pdf), in Proc. ACM/IEEE Design Automation Conf., Los Angeles, June 2000, pp. 477-482.
• O. Coudert, I. L. Markov, C. Meinel and E. Sentovich, ``Web-based frameworks to enable CAD R&D'', in Proc. ACM/IEEE Design Automation Conf., Los Angeles, June 2000, p. 711-712.
• A. A. Kennings and I. L. Markov, "Analytical Minimization of Half-Perimeter Wirelength", (.ps), (.pdf), (.slides) in Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., Jan. 2000. , pp. 179-184 (BPA nominee).
• A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Improved Algorithms for Hypergraph Bipartitioning", (.ps), (.pdf), (.slides) in Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., Jan. 2000. , pp. 661-666.

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• A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, "Hypergraph Partitioning for VLSI CAD: Methodology for Reporting, and New Results", (.ps), (.pdf) Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 349-354.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hypergraph Partitioning With Fixed Vertices", (.ps), (.pdf) Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 355-359.
• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-Case Placers for Standard-Cell Layout", (.ps), (.pdf), (slides) Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 90-96.
• C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, "Partitioning With Terminals: A `New' Problem and New Benchmarks", (.ps), (.pdf), (slides) Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 151-157.
• R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, "Function Smoothing with Applications to VLSI Layout", (.ps), (.pdf), (slides) Proc. IEEE/ACM Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228. (BPA nominee).

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• A. E. Caldwell, A. B. Kahng and I. L. Markov, "Relaxed Partitioning Balance Constraints in Top-Down Placement" (.ps), (.pdf), (slides) Proc. IEEE ASIC Conference, September 1998, pp. 229-232.  
• A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Watermarking Techniques for Intellectual Property Protection" (.ps), (.pdf) Proc. ACM/IEEE Design Automation Conference, San Francisco, June 1998, pp. 776-781. 
• A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Robust IP Watermarking Methodologies for Physical Design" (.ps), (.pdf), (slides) Proc. ACM/IEEE Design Automation Conference, San Francisco, June 1998, pp. 782-787. 
• A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement" (.ps), (.pdf), (slides) Proc. ACM/IEEE Intl. Symp. on Physical Design, Monterey, April 1998, pp. 4-11. 
• A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, "Implications of Area-Array I/O for Row-Based Placement Methodology"(.ps), (.pdf), (slides) Proc. IEEE Symp. on IC/Package Design Integration, Santa Cruz, February 1998, pp. 93-98. 

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• C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov and K. Yan "Quadratic Placement Revisited" (.ps), (.pdf), (slides) Proc. ACM/IEEE Design Automation Conference, Anaheim, June 1997, pp. 752-757.  (BPA nominee)
• C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet and K. Yan, "Faster Minimization of Linear Wirelength for Global Placement" (.ps), (.pdf), (slides) Proc. ACM/IEEE Intl. Symp. on Physical Design, Napa, April 1997, pp. 4-11. 

1. J. A. Roy, D. A. Papa, J. F. Lu, A. N. Ng, I. L. Markov, ``Tool Development For Multi-Million Gate Designs'' (.pdf), workshop on Electronic Design Processes, 2005.
2. I. L. Markov et al., ``Handling Symmetries in Computational Fields'', discussion panel at SymCon 2004.
3. I. L. Markov, ``Floorplacement'', invited talk at a one-day research symposium organized by Intel Corp. in Haifa, Israel, July 2004.
4. I. L. Markov, ``Handling Structure in Boolean Satisfiability'', a 3-lecture tutorial at a summer school on Symmetries in Constraint-Satisfaction Problems at St. Andrews, Scotland, June 2004.
5. S. N. Adya and I. L. Markov, ``Unification of Placement and Floorplanning'', Synplicity Inc., Sunnyvale, CA, May 2004.
6. I. L. Markov, ``Simulation and Synthesis of Quantum Circuits'', (.pdf), Theory Seminar, Columbia University, CS Department, March 2004.
7. I. L. Markov, ``Simulation and Synthesis of Quantum Circuits'' Distinguished Talk in Quantum Information Processing, National Institute of Standards(NIST), January 2004.
8. I. L. Markov, ``Symmetry-breaking for Boolean Satisfiability and 0-1 ILP,'' Electronic Systems Seminar, UC Berkeley, November 2003.
9. I. L. Markov, ``Symmetry-breaking for Boolean Satisfiability,'' Theory Seminar, Universita Roma I, La Sapienza , May 2003.
10. J. P. Hayes and I. L. Markov, ``Simulation, Synthesis and Testing of Quantum Circuits'' (.ppt), DARPA QuIST annual research review, Beverly Hills, CA, June 2003.
11. P. Kudva and I. L. Markov, ``Benchmarking For Physical Synthesis'' (.ppt), IWLS, Laguna Beach, CA, May 2003
12. I. L. Markov, ``Bookshelf.EXE'' (slides) GSRC Workshop, Pittsburg, PA, Dec 2002.
13. I. L. Markov and J. P. Hayes, ``Simulation and Synthesis of Quantum Circuits'' (.ppt), DARPA QuIST annual research review, Cambridge, MA, Sept 2002.
14. I. L. Markov, ``Bookshelf.EXE: Executable Extensions to the GSRC Bookshelf'', (slides) The GSRC Symposium, New Orleans, LA, June 2002.
15. I. L. Markov and P. G. Villarrubia, ``Lazy Timing-Driven Placement'', IBM Annual All-site Meeting, Fishkill, NY, April, 2001.
16. I. L. Markov, ``Large-scale Optimization in VLSI CAD'', CAD Seminar, UC Berkeley, November 2000
17. A. E. Caldwell, A. B. Kahng and I. L. Markov, ``CAD-IP Reuse via the Bookshelf for Fundamental VLSI CAD Algorithms'', (.ppt), (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., Los Angeles, June 2000.
18. I. L. Markov ``The MARCO/GSRC Bookshelf For Fundamental VSLI CAD Algorithms'' (ppt) The Gigascale Silicon Research Center, Annual Review, San Jose, Dec 9, 1999;
19. A. B. Kahng, A. E. Kennings, I. L. Markov, "Effective Optimization Strategies for Large-scale Placement", Sixth SIAM Conference on Optimization (.ps), Minisymposium on Optimization in Circuit Placement for VLSI , Atlanta, Georgia, May, 1999.

1. I. L. Markov and Y. Shi, ``Simulating quantum computation by contracting tensor networks'', Quantum Information and Computation (QIP), Paris, France 2006.
2. I. L. Markov, ``Algebratic Structure Helps in Finding and Using Almost-Symmetries'', Symmetries in Constraints (SymCon), Sitges, Spain 2005.
3. Y. Oh, E. Ernst, K. A. Sakallah, I. L. Markov, ``Constructive Logic and Layout Synthesis Does Not Work'', IWLS, pp. 367-374, Lake Arrowhead, CA, June 2005.
4. K.-H. Chang, I. L. Markov, V. Bertacco, ``Post-Placement Rewiring by Exhaustive Search for Functional Symmetries'', (.pdf) IWLS, pp. 469-476, Lake Arrowhead, CA, June 2005.
5. A. Ramani and I. L. Markov, ``Automatically Exploiting Symmetries in Constraint Programming'', (.pdf) Symmetries in Constraints (SymCon) Toronto 2004.
6. K. M. Svore, A. W. Cross, A. V. Aho, I. L. Chuang, I. L. Markov, "Toward a software architecture for quantum computing design tools" (.pdf), Workshop on Quantum Programming Languages, July 2004, Turku, Finland.
7. G. F. Viamontes, I. L. Markov and J. P. Hayes, ``Is Quantum Search Practical?'' (.pdf), (slides), IWLS, Temecula Creek CA, June 2004, pp. 478-485.
8. K. N. Patel, I. L. Markov and J. P. Hayes, ``Efficient Synthesis of Linear Reversible Circuits'' (.pdf), (slides), IWLS, Temecula Creek CA, June 2004, pp. 470-477.
9. J. A. Roy, I. L. Markov and V. Bertacco, ``Restoring Circuit Structure from SAT Instances'', (.pdf), (slides), IWLS, Temecula Creek CA, June 2004 , pp. 361-368.
10. H. H. Chan and I. L. Markov, ``Symmetries in Rectangular Block-Packing'' (.pdf), Intl. Workshop on Symmetry in Constraint-Satisfaction Problems (SymCon), 2003, pp. 27-40.
11. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Symmetry-Breaking for Pseudo-Boolean Formulas'' (.pdf), Intl. Workshop on Symmetry in Constraint-Satisfaction Problems (SymCon), 2003, pp. 1-12.
12. K. N. Patel, I. L. Makov, and J. P. Hayes, ``Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models,'' (.pdf) (.ppt) IWLS, pp. 59-64, Laguna Beach, CA, May 2003.
13. I. L. Markov, ``An Introduction to Reversible Circuits'' (.pdf), (.ppt), IWLS, Laguna Beach, CA, May 2003 (invited)
14. J. A. Roy and I. L. Markov, ``On Sub-optimality and Scalability of Logic Synthesis Tools,'' (.pdf) (.ppt) IWLS, Laguna Beach, CA, May 2003.
15. V. V. Shende, A. K. Prasad, K. N. Patel, I. L. Markov, and J. P. Hayes (.pdf) (.ppt) ``Scalable Simplification of Reversible Logic Circuits,'' IWLS, Laguna Beach, CA, May 2003.
16. F. A. Aloul, I. L. Markov, K. A. Sakallah, ``Symmetry-breaking for Boolean Satisfiability: The Mysteries of Logic Minimization'' Intl. Workshop on Symmetry on Constraint Satisfaction Problems (SymCon), slides, paper, Ithaca, NY, Sept 2002, pp. 37-46.
17. V. V. Shende, A. K. Prasad, I. L. Markov and J. P. Hayes, ``Synthesis of Optimal Reversible Logic Circuits'', IWLS, slides, paper, New Orleans, LA, June 2002, pp. 125-130. Available online as http://xxx.lanl.gov/abs/quant-ph/0207001 .
18. F. A. Aloul, I. L. Markov, K. A. Sakallah, ``Efficient Gate and Input Ordering for Circuit-to-BDD Conversion'', slides, paper, IWLS, New Orleans, LA, June 2002, pp. 137-142.
19. D. B. Motter and I. L. Markov ``Overcoming Resolution-Based Lower Bounds for SAT Solvers'' slides (.ps, .pdf) IWLS, New Orleans, LA, June 2002, pp. 373-378.
20. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``PBS: A Pseudo-Boolean Solver and Optimizer", slides (.ppt, .pdf), paper, SAT, Cincinnati, OH, May 2002, pp. 346-353.
21. D. B. Motter and I. L. Markov, ``On Proof Systems Behind Efficient SAT Solvers'', slides (.ppt, .pdf), SAT, Cincinnati, OH, May 2002, pp. 206-213.
22. F. A. Aloul, A. Ramani, I. L. Markov and K. A. Sakallah, ``Solving Difficult SAT Instances In The Presence of Symmetry'', slides (.ppt, .pdf), SAT, Cincinnati, OH, May 2002, pp. 338-345.
23. D. B. Motter and I. L. Markov, ``A Breadth-First Search For Satisfiabiliy'', slides (.ppt, .pdf) ALENEX, San Francisco, CA, January 2002
24. F. A. Aloul, I. L. Markov and K. A. Sakallah ``MINCE: A Static Global Variable-Ordering for SAT and BDD'', IWLS, Lake Tahoe, CA, June 2001 sildes (.pdf)
25. I. L. Markov and P. G. Villarrubia, ``Methods for Top-Down Timing-Driven Placement'', 2nd IBM ACAS Conference, Austin, TX, February, 2001
26. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning", (slides) ACM/SIAM Workshop on Algorithm Engineering and Experimentation (ALENEX), Jan. 1999

Quantum Physics Abstracts @http://xxx.lanl.gov/ quant-ph

1. http://xxx.lanl.gov/abs/quant-ph/0207001
2. http://xxx.lanl.gov/abs/quant-ph/0208003
3. http://xxx.lanl.gov/abs/quant-ph/0211002
4. http://xxx.lanl.gov/abs/quant-ph/0302002
5. http://xxx.lanl.gov/abs/quant-ph/0303039
6. http://xxx.lanl.gov/abs/quant-ph/0308033
7. http://xxx.lanl.gov/abs/quant-ph/0308045
8. http://xxx.lanl.gov/abs/quant-ph/0309060
9. http://xxx.lanl.gov/abs/quant-ph/0401162
10. http://xxx.lanl.gov/abs/quant-ph/0403114
11. http://xxx.lanl.gov/abs/quant-ph/0404003
12. http://xxx.lanl.gov/abs/quant-ph/0405001
13. http://xxx.lanl.gov/abs/quant-ph/0406176

Technical Reports @UMich

1. F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Faster SAT and Smaller BDDs via Common Function Structure'', CSE-TR-445-01, University of Michigan, December 2001. (.pdf)
2. A. Ramani and I. L. Markov, ``The FMSAT Satisfiability Solver: Hypergraph Partitioning Meets Boolean Satisfiability'', CSE-TR-448-02, University of Michigan, February 2002.
3. F. A. Aloul, I. L. Markov and K. A. Sakallah, ``Generic ILP versus Specialized 0-1 ILP: An Update'', CSE-TR-461-02.pdf, University of Michigan, August 2002.
4. Fadi A. Aloul, Arathi Ramani, Igor L. Markov and Karem A. Sakallah, ``Solving Difficult Instances of Boolean Satisfiability in the Presence of Symmetry'' (.pdf), CSE-TR-463-02, University of Michigan, September 2002.
5. H. H. Chan and I. L. Markov, ``Practical Slicing and Non-slicing Block-Packing without Simulated Annealing'', CSE-TR-487-04, University of Michigan, December 2004. (.pdf)

Technical Reports @UCLA

1. C.J. Alpert, T. Chan, D.J.-H. Huang, I. Markov, and K. Yan, Quadratic Placement Revisited, TR 97-48, UCLA, UCLA Mathematics Department, September 1997
2. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, and Kenneth Yan, Faster Minimization of Linear Wirelength for Global Placement, TR 97-49, UCLA, Mathematics Department, September 1997

1. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal End-Case Partitioners and Placers for Standard-Cell Layout" (.ps), (.pdf) TR-990013, March 1999.
2. A.E. Caldwell, A.B. Kahng and I.L. Markov, "Design and implementation of move-based partitioners" (.ps), (.pdf) TR-990015, March 1999.
3. A.A. Kennings and I.L. Markov, "Analytic Placement of Hypergraphs - I" (.ps), (.pdf) TR-990020, March 1999.
4. A. E. Caldwell and I. L. Markov, "Hierarchical Whitespace Allocation", (.ps), (.pdf) TR-200002, January 2000.