¡@	SIS script.rugged			BDS 1.2			BDS-pga 2.0			FBDD 1.0
Circuit	Runtime	S.C. Area	FPGA Area	Runtime	S.C. Area	FPGA Area	Runtime	S.C. Area	FPGA Area	Runtime	S.C. Area	FPGA Area
9symml	3900	159	62	240	346	110	240	294	98	232	57	15
C1355	3000	420	78	650	442	76	620	446	79	239	431	79
C17	0	7	2	0	8	2	0	8	2	13	11	2
C1908	4000	434	111	1300	451	122	1290	468	131	819	416	110
C2670	2900	585	182	-	-	-	-	-	-	1519	592	171
C3540	8300	1063	388	1510	1102	350	2400	1065	343	17381	1124	336
C432	31700	178	67	250	223	77	1490	329	97	320	289	71
C499	3000	420	78	1480	435	81	1450	433	78	170	427	79
C5315	4400	1342	455	-	-	-	-	-	-	2171	1385	456
C6288	13600	2810	509	2800	3066	601	2230	2995	538	527	3107	494
C7552	29900	1794	451	4710	2103	474	5450	2021	511	4604	1918	477
C880	1100	357	119	1070	353	107	1060	393	119	419	372	100
alu2	9800	302	126	340	345	99	360	319	78	3705	495	151
alu4	43700	599	230	2630	958	269	2310	994	297	6853	1037	312
apex6	1100	620	200	970	824	250	530	758	255	819	755	241
apex7	300	206	66	280	272	76	140	245	90	218	271	79
b1	0	8	3	0	9	3	0	10	3	10	7	3
b9	100	116	44	110	113	44	70	116	48	132	118	40
c8	200	105	39	110	162	40	50	107	36	166	132	41
cc	100	55	19	70	65	23	30	62	25	29	57	19
cht	100	143	39	130	166	39	60	147	38	24	149	38
cm138a	100	25	9	10	34	9	0	37	9	22	36	9
cm150a	100	45	13	3300	37	13	3320	37	13	100	38	13
cm151a	0	19	8	0	35	8	0	19	7	49	20	8
cm152a	0	16	6	240	22	7	10	16	6	32	16	6
cm162a	100	39	13	20	42	12	0	45	14	34	39	12
cm163a	0	35	10	10	40	12	10	44	12	23	39	12
cm42a	100	31	10	10	39	10	10	38	10	15	37	10
cm82a	0	18	4	0	24	4	0	20	4	18	19	4
cm85a	100	42	14	20	45	12	10	45	12	60	45	14
cmb	0	47	17	30	52	16	10	54	19	40	61	16
comp	200	105	33	28070	141	30	27970	141	31	161	116	31
cordic	100	52	14	60	75	20	90	79	19	181	67	16
count	100	111	45	100	133	45	50	134	39	39	137	45
cu	100	51	18	40	58	20	10	62	20	58	55	18
dalu	29000	751	277	-	-	-	-	-	-	1883	1241	355
decod	100	44	18	30	53	18	20	44	18	23	44	18
des	38800	2852	1130	-	-	-	6100	4015	1340	8224	3569	1137
example2	700	280	106	320	364	119	150	332	122	213	325	113
f51m	200	88	23	40	86	27	30	99	23	65	108	25
frg1	1000	125	49	280	110	37	230	110	40	214	49	19
frg2	5800	637	250	1870	1066	395	1070	1163	445	1449	804	290
i1	200	47	16	30	51	18	10	51	17	25	47	16
i10	139000	1929	682	4210	2581	787	3110	2496	849	4584	2211	712
i2	1800	171	72	4550	180	71	1510	206	72	4086	172	69
i3	300	107	46	170	107	46	120	103	46	109	107	46
i4	61500	181	70	240	183	71	410	200	74	866	181	70
i5	300	211	66	180	261	73	180	238	75	120	214	67
i6	700	346	113	560	526	145	320	462	144	92	382	107
i7	1000	560	173	1670	684	222	520	681	201	151	473	169
i8	5700	887	338	3130	1295	457	2420	1297	534	2401	1013	367
i9	1700	503	193	2030	730	280	660	683	276	369	622	194
k2	16400	1013	403	-	-	-	-	-	-	9838	1003	382
lal	300	90	30	110	102	35	50	109	42	96	95	32
majority	0	11	2	0	12	3	0	11	3	16	11	2
mux	100	38	13	3000	37	13	3030	37	13	100	37	13
my_adder	300	166	32	4090	212	42	2010	177	32	42	141	32
pair	5400	1377	440	4110	1528	476	3420	1482	478	1465	1582	488
parity	100	44	5	0	40	5	0	40	5	19	44	5
pcle	100	64	20	40	68	20	10	68	20	24	65	20
pcler8	100	88	29	60	90	30	20	90	30	41	87	29
pm1	100	43	18	30	51	18	20	51	21	45	50	20
rot	1900	595	213	10360	738	248	9850	643	225	728	633	222
sct	300	68	17	80	96	29	40	91	32	81	90	23
t	100	7	244	0	10	2	0	7	2	15	7	2
t481	24400	612	244	1130	33	5	-	-	-	15494	35	5
tcon	0	19	8	10	45	8	10	19	8	12	19	8
term1	1400	152	40	360	204	66	200	180	60	1158	278	89
too_large	5397100	264	105	41300	2034	760	174390	1813	695	3918	1684	507
ttt2	500	194	67	180	236	66	100	216	68	277	239	70
unreg	100	74	33	80	103	32	50	99	32	23	97	32
vda	9800	525	226	1660	690	270	590	865	366	1334	549	220
x1	700	267	113	720	355	141	400	335	137	633	384	133
x2	100	42	16	40	46	17	20	57	16	56	67	17
x3	1600	651	220	1020	692	209	670	754	232	580	703	217
x4	800	346	131	630	526	161	300	493	175	339	400	129
z4ml	100	33	9	0	31	6	10	40	8	28	32	6
Total	5911800	28859	9782	¡@	¡@	¡@	¡@	¡@	¡@	102438	33769	10005
BDS Total	¡@	¡@	¡@	138880	28475	8489	¡@	¡@	¡@	78803	25980	7504
BDS-pga Total	¡@	¡@	¡@	¡@	¡@	¡@	263320	31839	10057	71533	29515	8636
Norm	57.7X	85.5%	97.8%	1.8X	109.6%	113.1%	3.7X	107.9%	116.5%	1X	100.0%	100.0%
For SIS, script.rugged was used.
For BDS, BDS-pga and FBDD, default options were used.
Data is not reported for circuit runs that crashed or did not complete in less than 4 hours.
For both BDS and BDS-pga, 7.7% of circuits failed to synthesize.
Praetor was used for technology mapping to FPGA
SIS mapper and lib2.genlib were used for technology mapping to Standard Cell