¡@	SIS script.algebraic			FBDD 1.0
Circuit	Runtime	S.C. Area	FPGA Area	Runtime	S.C. Area	FPGA Area
b01.blif	0	67744	13	53	78416	12
b02.blif	0	41296	4	28	45008	4
b03.blif	100	266336	52	114	275616	51
b04.blif	800	885312	174	971	919648	162
b05.blif	1200	861648	220	1375	955840	222
b06.blif	100	82592	10	44	98832	10
b07.blif	400	636144	140	348	673264	132
b08.blif	200	266800	48	285	313664	56
b09.blif	100	264944	48	109	289072	50
b10.blif	200	283968	78	240	310880	68
b11.blif	800	740544	174	1002	928928	168
b12.blif	2700	1659728	402	5178	1814704	387
b13.blif	400	540096	97	256	592992	89
b14.blif	77900	6057520	1626	31755	6357728	1600
b14_1.blif	50800	6895504	1931	120532	7015680	1827
b15.blif	11553500	10607040	3094	51754	10582912	2770
b15_1.blif	261200	10691488	3185	64534	11054800	2899
b17.blif	-	-	-	173908	32826608	8563
b17_1.blif	-	-	-	132413	34734112	9182
b20.blif	502600	12562800	3295	76864	13474560	3276
b20_1.blif	351300	13910720	3887	58732	14802064	3706
b21.blif	542200	12728448	3364	86307	13211008	3309
b21_1.blif	379100	14544544	4159	54799	15246576	3913
b22.blif	1739700	19035136	5029	68058	20033200	4938
b22_1.blif	1234600	21203408	5890	62800	22033968	5658
Total	¡@	¡@	¡@	992459	208670080	53052
SIS Total	16699900	134833760	36920	686138	141109360	35307
Norm	24.3X	95.6%	104.6%	1.0X	100.0%	100.0%
For SIS, b17 and b17_1 could not complete in under 4 hours.
Praetor was used for technology mapping to FPGA
SIS mapper and lib2.genlib were used for technology mapping to Standard Cell