FPD'96 features exiting presentations on advanced technology, novel applications of FPGAs, new CAD developments, and commercial products. We anticipate this year's workshop to be one of our best ever.
Following the tradition of other FPGA-related workshops, FPD'96 will feature two styles of talks: lectures and posters. In both cases, talks will be accompanied by written papers that will appear in the workshop proceedings. The workshop features a number of excellent submitted and invited presentations, as well as two exciting keynote speeches by leading researchers in their fields:
In addition to the above presentations, because this year's workshop is being held at the University of Toronto, FPD'96 will also feature a number of talks marked as "Cider Seminars". Cider seminars are a long-standing tradition in the Computer Engineering Group at the U. of Toronto, in which researchers meet over a cauldron of hot apple cider to critique research in progress. "Ciders" are not accompanied by written papers, but copies of slides will be provided.
There will also be vendor exhibits at FPD '96, on Tuesday, May 14. Finally, immediately after the workshop a special full-day course will be offered, in which participants will have the opportunity to gain practical experience implementing digital circuits (in VHDL) in (Xilinx) FPGAs. The course was developed by the Canadian Microelectronics Corporation, and is hosted by U. of Toronto. Full details are available at http://www.cmc.ca/Training/Rapid/workshop.html .
FPD '96 Industrial Sponsors:
Xilinx, Altera, Actel
FPD '96 Sponsors:
Information Technology Research Centre, Canadian Microelectronics Corporation
8:50 - 9:00 - Opening Remarks
Session 1 - CAD Algorithms
Chair - Mohamad Sawan, E.P. Montreal
9:00 "Placement and Routing for Three-Dimensional FPGAs," M. Alexander, J. Cohoon, J. Colflesh, J. Karro, E. Peters and G. Robins, U. Virginia
9:20 [Cider talk] "Technology Mapping Issues for Hybrid FPGA Architectures," A. Kaviani, U. Toronto
9:40 [Cider talk] "System Design Experience with Modern CAD Tools," Naraig Manjikian, U. Toronto
10:00 - 11:00 Coffee & Posters on Novel Applications
Poster: "A Multiprocessor Implementation of a Wavelet Transform," C. Achour, J. Davidson, and J.L. Houle, E.P. de Montreal
Poster: "Implementation of a Multichannel PC-Controlled Stimulus Generator," S. Mallette, M. Sawan, E.P. de Montreal, and P.A. Fortier, U. Ottawa
Poster: "Fuzzy Logic Processor," C.E. Rabel, J. Davidson, and M. Sawan, E.P. de Montreal
Session 2 - Novel Applications and Technology I
Chair - Stephen Brown, U. Toronto
11:00 "FPGA Fast Counter Design," G. Yasar, Y. Tsyrkina and D. Thygesen, IBM Microelectronics
11:20 [Cider Talk] "Using randomly generated realistic circuits for the evaluation of new field-programmable architectures," M. Hutton, U. Toronto
11:40 - 12:30 Keynote Speech: "Run-Time Reconfiguration: Evolution of a New Strategy for Computing," Brad Hutchings, Brigham Young University
12:30 - 2:00 - Lunch
Session 3 - Technologies and Architectures I
Chair - Jonathan Rose, U. Toronto
2:00 "Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density," A. Dehon, MIT
2:20 "Field Programmable Smart Pixel Arrays," T. Szymanski, McGill U.
2:40 [Cider talk] "The Configurable Memory Research Project at UofT," S. Wilton, U. Toronto
3:00 - 4:00 - Coffee & Posters on FPGA Architecture
Poster: "DSP Circuit Structure and FPGA Architectural Requirements for a DSP FPGA," Dipankar Talukdar and Ramalingam Sridhar, State University of New York at Buffalo
Poster: "Enhancements to Third-Generation FPGA Architecture Support," B. Fawcett, Xilinx
Poster: "The XC8100: A Synthesis-Friendly, OTP FPGA Family," B. Fawcett, Xilinx
Session 4 - Advanced Architectures
Chair - Tim Southgate, Altera
4:00 "Introduction to Laser-Programmed Gate Array Technology," M. Ayukawa, Chip Express
4:20 "A Reconfigurable Architecture for Digital Signal Processing and Neurocomputation: Application and Design Considerations," G.K. Rosendahl, R.D. McLeod, and H.C. Card, U. Manitoba
4:40 "The XC6200: A Microprocessor-Oriented FPGA," C. Patterson, Xilinx U.K.
5:00 - 6:00 - Free Time
6:00 - 8:00 - Dinner
Session 5 - FPGA Interconnect
Chair - Stephen Brown, U. Toronto
9:00 "A Hierarchical Routing Structure Complementary with a Fine-Grained FPGA Architecture," S. Beavis, Pilkington Micro-Electronics
9:20 "High Performance FPGA Interconnect Delay Estimation," SeungJu Yoo and K. Choi, Seoul National University, Korea
9:40 [Cider talk] "FPGA Global Routing Architectures," V. Betz, U. Toronto
10:00 - 11:00 - Coffee & Posters on Novel Applications
Poster: "FPGA Implementation of Discrete Cosine Transforms 4x4,8x8,16x16," A. Kassem, J. Davidson, and J.L. Houle, E.P. de Montreal
Poster: "A Hamming Decoder for Single Error Detection and Correction," S. Mounier and M. Sawan, E.P. de Montreal
Poster: "A Hand-held Controller Dedicated to Implantable Stimulators," S. Robin and M. Sawan, E.P. de Montreal
Session 6 - Technologies and Architectures II
Chair - Stephen Brown, U. Toronto
11:00 "A New Field-Programmable Mixed-Signal Array and Its Applications," C. Zhang, A. Bratt and I. Macbeth, Pilkington Micro-Electronics
11:20 - 12:00 Keynote Speech: "Field-Programmable Analog Arrays: A Status Report," Glenn Gulak, U. Toronto
12:00 - 1:30 - Lunch
Session 7 - Novel Applications and Technology II
Chair - Jacob Davidson, U. Quebec a Montreal
1:30 "Rapid Prototyping of Artificial Neural Networks," R. Ng, Xilinx, and R. McLeod, U. Manitoba
1:50 "Multi-Rate Clocking for Reconfigurable Logic Arrays," A. Wenban and G. Brown, Cornell U.
2:10 "Simulation of Queueing Systems in FPGAs," P. Chong and W. Loucks, U. Waterloo
2:30 - 3:30 - Coffee & Posters
Session 8 - Multi-FPGA Systems
Chair - Sinan Kaptanoglu, Actel
3:30 [Cider Talk] "Wiring Issues for Multi-FPGA Systems," M. Khalid, U. Toronto
3:50 "Rapid Prototyping Systems Incorporating FPGAs and FPICs," H. Nyugen and R. McLeod, U. Manitoba, and C. Swanson, IRIS Systems
4:10 "Bounds for Multi-Terminal Net Implementations on FPICs," D. Bhatia, U. Cincinnati, and J. Haralambides, Barry University
4:30 Workshop Ends
Once you reach the Lester B. Pearson International Airport in Toronto, you can travel downtown via any of three methods: 1. airport limousine, 2. airport TAXI, or 3. airport bus. Limousines are about $40 CDN, and TAXI's are slightly cheaper. The bus costs around $15 CDN. If you take the bus make sure that it is the bus to the downtown hotels, and not the bus to the subway system (you can still take the subway to the downtown hotels, but that is much less convenient than taking the bus directly to your hotel).
There are several hotels near the University of Toronto campus. A suggested hotel, within a short TAXI ride of the campus, is given below, but feel free to use whatever hotel you prefer. Please contact the hotel of your choice directly. Those interested in the lowest prices available can opt to stay in a student residence on campus; contact information for a student residence that is very close to the workshop site is available at http://www.eecg.toronto.edu/~brown/residence.html .
Delta Chelsea Inn
33 Gerrard Street West
Toronto, Canada
Reservations can be made by contacting the hotel reservation department directly at (416) CHELSEA (243-5732), by calling toll-free from Canada or the US 1-800-CHELSEA, or on the WEB at http://www.deltahotels.com/canada.html. The workshop rate is $109 per night (single or double), but this rate is guaranteed only until April 19; give the group name University of Toronto-ITRC. If you are asked for a "Q-name," it is GFITR.
Name: _______________________________________________________________
Company/University: _________________________________________________
Title: ______________________________________________________________
Address: ____________________________________________________________
City: _____________________ Country: _______________ ZIP: ___________
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Registration Fees (Includes All Meals)
Please check if you will be attending the dinner on Monday: Yes ___ No ___
Advance (Through May 1) Late (After May 1/On-Site)
Regular __ $225 CDN, $170 USD __ $250 CDN, $185 USD
Student __ $100 CDN, $75 USD __ $125 CDN, $90 USD
Dietary restrictions (if any): ______________________
Special needs: _____________________________________
The registration fee includes the workshop proceedings and all meals (i.e., 2 breakfasts, 2 lunches, and 1 dinner), and refreshments during breaks.
Note: Hotel reservations must be made directly with the Hotel of your choice (see above).
The only acceptable forms of payment are checks (personal, company, and certified/bank checks) either in Canadian funds drawn on a Canadian bank, or in US funds drawn on a US bank. Checks are to made payable to "Information Technology Research Center" (credit cards will not be accepted). Payment should accompany your registration. No FAX or Email registrations will be processed.
Please mail your payment (with checks) along with the registration form to:
Cancelations must be in writing and must be received by April 30, 1996.