The VTVT Group has developed a standard-cell library targeting the TSMC-0.25um, 2.5-volt CMOS process available via MOSIS. The library can be used with Synopsys synthesis tools and the Cadence Silicon Ensemble Place/Route tool. All of the cells can be viewed and edited using the Cadence Virtuoso layout editor. The cell library requires NCSU design kit or other kits that follow MOSIS design rules. Since MOSIS DEEP design rules are used for our cell library, the NCSU design kit has been modifed slightly and is included in our distribution.
In this Release 2 of the VTVT Standard Cell library, which was released on November 1, 2003, we made the following addition and modification to the Release 1:
- Additional cells. The Release 2 contains 83 cells, compared with 36 in Release 1.
- Additional modification to the NCSU design rule check file. Now MOSIS's wide-metal rule is implemented.
The users of the Release 1 of the VTVT standard cell library, or those who downloaded the library prior to November 2003, are recommended to update their library by downloading Release 2.The package for our cell library includes:
- layouts of primitive cells
- Synopsys synthesis (.db) and VHDL simulation libraries
- LEF files for the PNR tool
- README file and a documentation for modification of the NCSU kit
- Other documentation, including the place and route flow we used to test the library.
List of Cells Distributed (Release 2, November 1, 2003):
The following 83 cells are distributed in this distribution:- Combinational cells:
- Inverters: inv_1, inv_2, inv_4 (the last digit denotes the drive strength.)
- Buffers: buf_1, buf_2, buf_4 (the last digit denotes the drive strength.)
- AND/NAND: and2, and3, and4, nand2, nand3, nand4 (drive strengths: 1, 2, and 4)
- OR/NOR: or2, or3, o4, nor2, nor3, nor4 (drive strength: 1, 2, and 4)
- Other combinational cells such as xnor2, xor2, mux2, mux3, mux4, etc.
- Sequential cells: (Various drive strengths, all high-active or rising-edge triggered)
- D flip-flop
- D flip-flop with asynchronous reset
- D flip-flop with asynchronous reset and set
- D flip-flop with asynchronous set and inverted output
- D flip-flop with asynchronous reset and set and serial scan input
- JK flip-flop with asynchronous reset and inverted output
- D latch
- D latch with asynchronous reset
- D latch with asynchronous reset and set
- Others:
- Inverting tristate buffers, high-enabled, (drive strength: 1, 2, and 4)
- Noninverting tristate buffers, high-enabled, (drive strength: 2)
- Clock drivers (drive strength: 8, 12, 16)
- Complete list
To Receive Our Standard Cell Library:The cell library is available to universities and not-for-profit institutions at no charge. A total of 161 universities worldwide, consisting of 73 U.S. universities and 88 international universities, have received our cell library by October 31, 2003. Companies can acquire the library for a nominal fee. For details, click here.
The universities and research institutions which have received our standard cell library are as follows: