Electronic Design Process Subcommittee of IEEE DATC

EDP 2007 Workshop

Organized in cooperation with ISPD ( www.ispd.cc )

April 12 and 13, 2007

Monterey Beach Hotel, Monterey, California

	2007 Workshop Press Clippings		The following are review and articles that appeared in various EDA related press: EDP 2007 issues call for papers: http://www.eetimes.com/showArticle.jhtml;jsessionid=QMJ2V14PQD1Y4QSNDLRCKHSCJUNN2JVN?articleID=193402976 IBM EDA director calls for 'prescriptive CAD': http://www.eetimes.com/showArticle.jhtml;jsessionid=QMJ2V14PQD1Y4QSNDLRCKHSCJUNN2JVN?articleID=199000715 Richard Goering on DFM re the Workshop. http://www.eetimes.com/showArticle.jhtml;jsessionid=CSHLZDT144AO2QSNDLOSKHSCJUNN2JVN?articleID=199200261 Gary Smith's review article of EDP 2007: ReviewsArticles/GSEDA_EDP.jpg Richard Goering’s covering on Power aspects of EDP 07: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199203947
Call For Papers		A printable PDF of the Workshop's Call-For-Papers (CFP) may be found here.
Prior Year Archives: 2006 2005 2004 2003 2002 2001 2000	For information on past EDPS Workshops, speakers, and presentations, visit one of the past Workshop archives.

EDPS 2007 Workshop Program:

Speaker	Affiliation	Title/Area of Talk
Wednesday, April 11, 2007
Registration
05:30-7:00 PM Evening Reception @ Captain’s Table
Thursday, April 12, 2007

08:30 AM - 09:10 AM Welcome and Keynote Address

Host: Bhanu Kapoor - Chair's Welcome and Opening Remarks

Leon Stok	IBM	Keynote Address: "Design Rules: From Restriction to Prescription" - Presentation
09:20 AM -11:10 AM Session 1: Power: The Designer Community Perspective Session Chair:
Herve Menager	CTO SoCDT NXP	Words of Power: Reusable, Holistic, Scalable Multi-voltage Design - Presentation
Mahesh Mehendale	Texas Instruments	“System-level considerations/tradeoffs in the design of SoCs for portable video applications” - Paper - Presentation
	Krisztián Flautner	ARM, Inc.	Lunch Talk: Cutting across abstractions... -Presentation
Milind Paddhye	Freescale, Inc	Power Management Design Challenges - Presentation
11:15 AM – 12:30 PM Session 2: Power: The Automation Perspective Session Chair:
	Marco Casale-Rossi	Synopsys	EDA to the Rescue of the Silicon Roadmap - Presentation
	Ed Huizbregts	Magma Design	“Should Power Management Govern Design Hierarchy?” - Presentation
	Holly Stump	Sequence Design	“Power Management Early in the Design Flow: Exploration to Implementation” - Presentation
12:30 – 1:30 PM Lunch Break

1:30 PM – 3:00 PM Session 3: Design for Manufacturing Session Chair:
	Gary Smith	GarySmithEDA	DFM Market Perspective
	Michael Smayling	Tela Innovations, Inc.	"DFM - It's all about Cost!" - Paper
	Sorin Dobre	QualComm, Inc.	DFM – The path toward maturity through innovation and consistent added value - Presentation
	Rajesh Raina	Freescale	Fitting DFM in your design flow - Paper- Presentation
3:15 PM – 5:00 PM Session 4: Design for Manufacturing Session Chair:
	Andrew Kahng	UC, San Diego	“A Technology Roadmap for DFM”
	Patrick Groeneveld	Magma Design	Analysis is from Venus, Synthesis from Mars: Scenes from a DFY marriage - Presentation
	Frank Schellenberg, Nick Cobb, Dragos Dudau, Raghu Chalisani James McKibbin, Steve McPherson	Mentor Graphics, Mercury Systems	Hardware Acceleration for DFM/RET: "Accelerating Design For Manufacturing (DFM) and the Electronic Design Process (EDP) using the Cell BE (tm) microprocessor architecture" - Paper
6:30 – 9:00 Dinner Banquet @ Monterrey Beach Resort Dinner Talk Host: Juan-Antonio Carballo
	Grant Martin	Tensilica	Dinner Talk: Multi-core ESL
Friday, April 13
08:30 AM - 09:10 AM Keynote Address Host: Juan-Antonio Carballo
Andrew Singer, CEO	Rapport, Inc.	Keynote Address: "1000-core" invited talk: "So Many Cores, So Little Time…”.
09:20 AM -12:00 AM Session 5: Multi-Core Programming Session Chair:
Shameem F. Akhter	Intel	Multi-core: 1, 2, 3 . . . of Computing
	JoAnn Paul	Virginia Tech..	Latency and Throughput are Dead
	Daya Nadamuni	GarySmithEDA	Concurrent Programming Crisis
	Patrick Madden	SUNY	40 Years of Amdahl's Law.
Ashok Vittal and H. K. Verma	Velogix	A 180 GFLOP/s, 15 GFLOP/W 500 million transistors FPGA in 90nm CMOS
	Frank Schirrmeister	Imperas	Multiprocessor Architectures: Software Programming Challenges and Solutions"
12:00 – 1:00 PM Lunch Break
	Juan-Antonio Carballo	Argon Venture	Lunch Talk: New Wave of Design Technology Venture Capital: the Global Start-up
1:30 PM – 3:30 PM Session 6: EDA Standards: Helping or Hurting Session Chair: Tony Luk, Cadence
	Sumit DasGupta	Si2	Standard Setting at Si2: A Synergistic, End-User Driven Approach
	Karen Bartleson	Synopsys, Inc.	"EDA Standards: The Way I See It"
	Dennis Brophy	Mentor, Inc.	Low-Power: Today’s Hot Topic
	Igor Markov	U. Michigan	New Data Exchange Standards Without New Parsers
*EDA Standards QA/Panel:* *Panelists: Karen Bartleson, Dennis Brophy, Igor Markov*
3:45 – 5:00 PM Session 7: More Power and DFM to you Session Chair:
	Kaushik Roy	Purdue University	Process Variation Tolerant Circuit Design
Srikanth Jadcherla	ArchPro Design Automation	Getting Power Management to Work
Shrikrishna Pundoor, R. Venkatraman	Texas Instruments India	An Efficient Method for Leakage Optimization in Timing Critical Designs
Jairam S., Venkatraman R., Jeff Rudolph, Udaykumar H., Jagdish Rao	Texas Instruments India	An Automated Core Power Network Closure Methodology

EDP 2007 Chairs:
General Chair:	Bhanu Kapoor
2007 Program Committee Chairs:	Patrick Madden, Dennis Sylvester
Publications Chair:	Kumar Venkatramani
Publicity and Web Chair:	Steve Grout

EDPS Executive Committee

Michael Bohm
(AccelChip)
Elaheh Bozorgzadeh
(UCI)
Juan-Antonio Carballo (IBM)

Arpana Dey (Cadence)
Steve Grout (Consultant)
Dwight Hill (Synopsys)

Takahide Inoue(STARC)
Andrew B. Kahng (UCSD)
John Lillis (UIC)

Gabe Moretti (Gabe on EDA)

Naresh Sehgal (Intel)
José Augusto Lima (Univ. of Minho)
Sandeep Shukla
(Virginia Tech)
Gary Smith (GarySmithEDA)
Kumar Venkatramani (SoftJin)
Bhanu Kapoor (ArchPro) Patrick Madden (SUNY) Bill Halpin (Synplicity)
Dennis Sylvester (U. Mich)

Steven Levitan (U. Pittsburg)

Patrick Groeneveld

Background on the EDPS Annual Workshop:

The Electronic Design Processes (EDP) Workshop provides a forum for a cross-section of the design community to discuss state-of-the-art electronic design processes and CAD methodologies. As the requirements and complexities of electronic design increase, past ad hoc approaches to design processes are proving inadequate. The workshop focuses on the facilitation and improvement of the overall design process, rather than on the functions of the individual tools themselves. Topics include interactions among and between tools and designers, the infrastructures supporting these interactions, and the frameworks in which these interactions take place.

General Information on EDPS:

The Electronic Design Process Subcommittee (EDPS) is a technical subcommittee of the IEEE Computer Society's Design Automation Technical Committee (DATC).

Objectives of the EDPS:

The EDPS focuses on design process for electronics products with respect to design, design technology, and design productivity for both today's and coming technologies.

Activities and Achievements:

To provide a forum for electronics designers and CAD/EDA technologists to work together on design process issues, the EDPS holds an annual workshop to discuss design and EDA process problems, plans, and research.

In addition, the EDPS often holds a Birds of a Feather (BOF) at annual Design Automation Conferences (DAC), and also meets at ICCAD. Contact the EDPS Steering Committee for details.

Electronic Design Process Email List:

The email list for general information and announcements on EDPS is edps-all @ eda-stds.org.
To join the email list for the IEEE DATC EDPS group, send a request to the sysop below.

EDPS chair: Bhanu Kapoor www.eda-stds.org/edps Group Sysop: Steve Grout

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Last updated March 18, 2007, by Steve Grout - EDPS Webmaster