CAD
 Seminar
 Series


This is the web page for the CAD Seminar Series (aka EE8370) at the Electrical & Computer Engineering Department, University of Minnesota. The Seminar consists of weekly presentations of graduate students, most of them working in the VLSI Electronic Design Automation (VEDA) group of professor Sachin Sapatnekar and in the VLSI Physical Design / Reconfigurable Computing group of professor Kia Bazargan.


Fall 2004

Meeting time and place: Every Wednesday, 11:10-11:55am in 5-120 (EE/Csci Bldg.)

OBS: This schedule is very preliminary and is subject to change. The day and the exact time has to be decided.

WEEK No.

DATE

PRESENTER

TITLE

ABSTRACT

PDF / PPT

2

Sept. 15

Prof. Chris Kim

(chriskim@ece.umn.edu)

 Variation Tolerant VLSI Design

 

 Variation Tolerant

3

Sept 22

Jaskirat Singh

(jsingh@ece.umn.edu)

 Robust Transistor Sizing by Geometric Programming

 

 

4

Sept. 29

Tianpie Zhang

(zhangt@ece.umn.edu)

Simultaneous Buffer and Shield Insertion to Reduce Crosstalk Noise

 

 

5

Oct. 06

Vidyasagar Nookala

(vidya@ece.umn.edu)

Wire Pipelining : Why, How, and Headaches

 

 

6

Oct. 13

Hushrav Mogal

(mhush@ece.umn.edu)

Three Dimensional Place and Route for FPGAs

 

 

 

7

Oct. 20

Pongstorn Maidee

(pongstor@ece.umn.edu)

Wave Pipelining

 

 

8

Oct. 27

Yong Zhan

(yongzhan@ece.umn.edu)

Fast Computation of the Temperature Distribution in VLSI Chips Using the Discrete Cosine Transform and Table Look-Up

 

 

9

Nov. 03

Wonjoon Choi

(wjchoi@ece.umn.edu)

Statistical Area Optimization of  Floorplanning

 

 

10

Nov. 10

Satish

(satish@ece.umn.edu)

HARP: Hard Wired Routing Pattern FPGAs

 

 

11

Nov. 17

Yan Feng

(yanfeng@ece.umn.edu)

Constrained Floorplanning Using Network Flows

 

 

12

Nov. 24

 

Haifeng Qian

(qianhf@ece.umn.edu)

 

 

 

13

Dec. 01

Sanjay Kumar

(sanjay@ece.umn.edu)

 

 

 

 

14

Dec. 08

TBD

 

 

 

 

 

Evaluating at WebCT (restricted access only)

 

Waiting List:

 

Kia Bazargan (kia@ece.umn.edu)

Sachin Sapatnekar(sachin@ece.umn.edu)


Send e-mail to all

Spring 2004

Meeting time and place: Every Friday 11:10-11:55am in 5-120 (EECsci Bldg.)

OBS: This schedule is very preliminary and is subject to change. Students who are new in this seminar or students who took this class and did not make a presentation before will be given priority.

WEEK No.

DATE

PRESENTER

TITLE

ABSTRACT

PDF / PPT

2

Jan. 30

Sachin Sapatnekar

(sachin@ece.umn.edu)

After Graduation: Degrees of Freedom

 

 

3

Feb. 06

Anup Sultania

(anups@ece.umn.edu)

Tradeoffs Between Leakage and Delay for Dual Tox Circuits

 

 

4

Feb. 13

Vidyasagar Nookala

(vidya@ece.umn.edu)

Full-chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-flop Insertion

 

paper / presentation

5

Feb. 20

Tianpei Zhang

(zhangt@ece.umn.edu)

A probabilistic approach  to buffer insertion

 

 

6

Feb. 27

Rupesh Shelar

(rupesh@ece.umn.edu)

A Predictive Distributed Congestion Metric and its Application to Technology Mapping

 

Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37\%, on an average, in track overflows as compared to conventional technology mapping.

paper / presentation

7

Mar. 10

Jaskirat Singh

(jsingh@ece.umn.edu)

SILCA : Semi - Implicit Linear - Centric Analysis for Fast-Yet-Accurate Time-Domain Simulation for VLSI Circuit with Strong Parasitic Couplings

TIME: 12:00-12:50pm

paper / presentation

8

Mar. 12

Yong Zhan

(yongzhan@ece.umn.edu)

Geometric Programming - CAD algorithm for multi-GHz RF circuits?

 

 

9

Mar. 19

Spring-break

 

 

 

10

Mar. 31

Haifeng Qian

(qianhf@ece.umn.edu)

Electrostatic discharge in  IC
List of papers

TIME: 1:40-2:30pm

paper / presentation

12

Apr. 07

WonJoon Choi

(wjchoi@ece.umn.edu)

Simultaneous Pin Assignment and Routing

TIME: 1:40-2:30pm

paper / presentation

13

Apr. 14

Bing Lu (binglu@ece.umn.edu)

CANCELLED

TIME: 1:40-2:30pm

 

14

Apr. 16

Cristinel Ababei

(ababei@ece.umn.edu)

 PAR

 

 

15

Apr. 28

Pongstorn Maidee

(pongstor@ece.umn.edu)

Integer  Program  Formulations of Global Routing  Problems

TIME: 1:30-2:30pm
Room:
4-178A

pdf / ppt

16

Apr. 30

Brent Goplen

(bgoplen@ece.umn.edu)

 

 

 

17

May
07

Bing Lu (binglu@ece.umn.edu)

Temperature-aware 3D global routing

TIME: 11:20-12:20pm

 

 

Evaluating at WebCT (restricted access only)

 

Waiting List:

 

Kia Bazargan (kia@ece.umn.edu)

Ximing Yang (yang0573@umn.edu)

Hongliang Chang (hchang@cs.umn.edu)

Shrirang Karandikar (srirang@ece.umn.edu)

Cristinel Ababei (ababei@ece.umn.edu)

 


Send e-mail to all

 


Fall 2003

Meeting time and place: Every Tuesday 10:00-10:50am in 4-146 (EECsci Bldg.)

WEEK No.

DATE

PRESENTER

TITLE

TOPIC

PDF / PPT

2

Sep. 9

Kia Bazargan

(kia@ece.umn.edu)

How to Make a  Presentation

Download template .ppt

 

3

Sep. 16

Yong Zhan

(yongzhan@ece.umn.edu)

Static Noise Analysis with Noise Windows

Signal  Integrity

pdf / ppt

4

Sep. 23

Vidyasagar Nookala

(vidya@ece.umn.edu)

A Linear Programming Based Solution to the Pipelined Interconnects Problem

 

 

5

Sep. 30

Haifeng Qian

(qianhf@ece.umn.edu)

Stochastic Linear Solvers
(Complete List of Presented Papers)

Non-classical Linear Solvers

pdf / ppt

 

Oct. 2

Sani Nassif (prof. Sachin's guest)

Challenges in the Design/Manufacturing Interface

 

pdf

6

Oct. 7

Brent Goplen

(bgoplen@ece.umn.edu)

Thermal Placement of 3D ICs

 

pdf / ppt

7

Oct. 14

WonJoon Choi

(wjchoi@ece.umn.edu)

Placement-Driven Technology Mapping for LUT-Based FPGAs

 

 

 

pdf / ppt

 

8

Oct. 21

Anup Sultania

(anups@ece.umn.edu)

 

Gate Leakage

pdf / ppt

 

9

Oct. 28

Hongliang Chang

(hchang@cs.umn.edu)

Statistical timing analysis considering spatial correlations using a single PERT-like traversal

SSTA

pdf / ppt

10

Nov. 4

Shrirang Karandikar

(srirang@ece.umn.edu)

Logic Decomposition During Technology Mapping

 

pdf1

pdf2

12

Nov. 18

Cristinel Ababei

(ababei@ece.umn.edu)

Placement Method Trageting Predictability Robustness and Performance

 

pdf / ppt

13

Nov. 25

Ning Dong (ningd@ece.umn.edu)

Linear model reduction and its applications in physical design

 

pdf / ppt

14

Dec. 2

Pongstorn Maidee

(pongstor@ece.umn.edu)

Routability-driven floorplanner with buffer block planning

Floorplanning

pdf / ppt

15

Dec. 9

Tianpei Zhang

(zhangt@ece.umn.edu)

 

 

 

 

 

Waiting List:

Girish Venkatraman (girish@ece.umn.edu)

Jaskirat Singh  (jsingh@ece.umn.edu)

Keith R. Bolson (krbolson@visi.com)

Christina D Godwin (godw0008@umn.edu)

Ting Mei (meiting@ece.umn.edu)

Divya Asokan (adivya@ece.umn.edu)

Sachin Sapatnekar (sachin@ece.umn.edu)

Not registered:

Cheng Wan (wan@ece.umn.edu)


Send e-mail to all

 


Spring 2003

Meeting time and place: Every Wednesday 2:30-3:20pm in 4-146 (EECsci Bldg.)

WEEK No.

DATE

PRESENTER

TITLE OF PRESENTED PAPER

2

Jan. 29

Rupesh Shelar (rupesh@ece.umn.edu)

Implications on PTL due to Technology Scaling

3

Feb. 5

Yong Zhan (yongzhan@ece.umn.edu)

Post Global Routing RLC Crosstalk Budgeting

4

Feb. 12

Hongliang Chang (hchang@cs.umn.edu)

Statistical Timing Analysis using Bounds and Selective Enumeration

5

Feb. 19

Anup Sultania (anups@ece.umn.edu)

P-map based detection of Sneak Paths in Pass Transistor Networks

6

Feb. 26

Vidyasagar Nookala (vidya@ece.umn.edu)

 

7

Mar. 5

Kekiang Wu (wuxx0223@umn.edu)

 

8

Mar. 12

Haifeng Qian (qianhf@ece.umn.edu)

Hierarchical Random Walk(s)

9

Mar. 19

=========> Holiday <=========

 

10

Mar. 26

Karthik Bhasyam (karthik@ece.umn.edu)

Cancelled

11

Apr. 2

WonJoon Choi (wjchoi@ece.umn.edu)

Incremental Placement for Timing Optimization

12

Apr. 9

Tianpei Zhang (zhangt@ece.umn.edu)

Estimation of signal arrival time in the presence of delay noise

13

Apr. 16

Zhe Wang (zhewang@mail.ece.umn.edu)

Simulation of substrate noise for SoC

14

Apr. 23

Karthik Bhasyam (karthik@ece.umn.edu)

An Integrated Algorithm for Memory Allocation and Assignment in High-level Synthesis

15

Apr. 30

Jaskirat Singh (jsingh@ece.umn.edu)

 

 

Waiting List:

Cheng Wan (wan@ece.umn.edu)

Brent Goplen (bgoplen@ece.umn.edu)

Shrirang Karandikar (srirang@ece.umn.edu)

Cristinel Ababei (ababei@ece.umn.edu)

Leave of absence:

Guoqiang Chen (gqchen@ece.umn.edu)


Fall 2002

Meeting time and place: Every Wednesday 2:30-3:20pm in 4-146 (EECsci Bldg.)

WEEK

PRESENTER

TITLE OF PRESENTED PAPER

2-Sept. 11

Shrirang Karandikar (srirang@ece.umn.edu)

Undisclosed topic of IBM Insider
"We know what you did last Summer!"

3-Sept. 18

Rupesh Shelar (rupesh@ece.umn.edu) 

Metrics for Routing Congestion for Logic Synthesis

4-Sept. 25

Cristinel Ababei (ababei@ece.umn.edu)

Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization

5-Oct. 2

Yong Zhan (yongzhan@ece.umn.edu)

Efficacy of Simplified 2D On-Chip Inductance Models

6-Oct. 9

Venkat Rajappan (venkatr@ece.umn.edu)

Worst-case Delay due to Crosstalk

7-Oct. 16

Hongliang Chang (hchang@cs.umn.edu)

A general probabilistic framework for worst case timing analysis

8-Oct. 23

Brent Goplen (bgoplen@ece.umn.edu)

 

9-Oct. 30

Tianpei Zhang (zhangt@ece.umn.edu)

 

10-Nov. 6

WonJoon Choi (wjchoi@ece.umn.edu)

Force Directed Placement

11-Nov. 13

Vidyasagar Nookala (vidya@ece.umn.edu)

 

12-Nov. 20

Haifeng Qian (qianhf@ece.umn.edu)

Random wolks on power networks

13-Nov. 27

Guoqiang Chen (gqchen@ece.umn.edu)

Partition-driven standard cell thermal placement

14-Dec. 4

Karthik Ranganathan (kar@ece.umn.edu)

Design Verification

15-Dec.11

Jaskirat Singh (jsingh@ece.umn.edu)

 


Spring 2002

Meeting time and place: Every Wednesday 2:30-3:20pm in 4-146 (EECsci Bldg.)

WEEK

PRESENTER

TITLE OF PRESENTED PAPER

1-Jan. 23

Brent Goplen (bgoplen@)

Cell-level placement for improving substrate thermal distribution

2-Jan. 30

Venkat Rajappan (venkatr@)

An Effective Capacitance Based Delay Metric for RC Interconnect

3-Feb. 6

Cristinel Ababei (ababei@)

On Routing Demand and Congestion Estimation for FPGAs

4-Feb. 13

WonJoon Choi (wjchoi@)

Timing Driven Placement using Physical Net Constraints

5-Feb. 20

Karthik Bhasyam (karthik@)

Efficient Circuit Clustering for Area and Power Reduction in FPGAs

6-Feb. 27

Xiaoyun Sun (xsun@)

Energy Consumption Ratio Test

7-March 6

Mahesh Ketkar (ketkar@)

Incorporating Functional Correlation Information in Crosstalk Analysis

8-March 13

Tianpei Zhang (zhangt@)

Optimized Pin Assignment for Lower Routing Congestion After Floorplanning Phase

9-March 20

--- spring break ---

 

10-March 27

Rupesh Shelar (rupesh@)

An integrated logical and physical design flow for deep submicron circuits

11-Apr. 3

Haitian Hu (hhu@)

 

12-Apr. 10

Shrirang Karandikar (srirang@)

Microprocessors: Past, Obsolete, Defunct and Current (more info here!!!)

13-Apr. 17

Wan Cheng (wan@)

 

14-Apr. 24

Yong Zhan (yongzhan@)