Reseach Interests Overview
  • CAD tools for VLSI / FPGA
  • Predictable, robust, and optimal synthesis
  • Reconfigurable computing
  • Embedded systems
Interests from a previous life: Analog VLSI (modeling, analysis, and optimization). Emphasis on oscillators and low power current-mode circuits. Information theory. Electromagnetic fields.

Physical Design for FPGA Fabrics: Placement and Routing
Place and route for 3D FPGAs: We present timing-driven partitioning and simulated annealing based placement algorithms together with a detailed routing tool for 3D FPGA integration. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool, which will be available on the web for the research community, as a platform to explore the potential benefits in terms of delay and wire-length that 3D technologies can offer for FPGA fabrics. Simulation experiments show on average a total decrease of 25% in wire-length and 35% in delay respectively, can be achieved over traditional 2D chips, when 10 layers are used in 3D integration.

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Place for 2D FPGAs: (Fast partitioning-based placement + Terminal allignment) + Low-temperature SA-based solution refinement = Four times shorter run-times, comparable to VPR circuit delays.

Related papers: C7

Multi-objective Optimization: Path-based Timing-driven Partitioning and Placement
We present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. A new objective function which incorporates a truly path-based delay component for the most critical paths is introduced. To avoid semi-critical paths from becoming critical, the traditional slack-based delay component is also included in the cost function. The proposed timing driven partitioning algorithm is built on top of the hMetis algorithm, which is very efficient. Simulations results show that delay is improved. The proposed timing-driven partitioning algorithm is again validated by integration into Capo placement tool.

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Robust Design: Placement for Robustness Predictability and Performance
We study the relationship between robustness, predictability and performance of VLSI circuits. It is shown that predictability and performance are conflicting objectives. Performance and robustness are statically conflicting objectives but they are statistically non-conflicting. We propose and develop means for changing a standard timing-driven partitioning-based placement algorithm in order to design more predictable and robust circuits without sacrificing much of performance.

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Statistical Design: Statistical Timing-driven Partitioning and Placement
Increasing circuit complexity and high demand for short time-to-market products force designers to adopt divide-and-conquer (partitioning-based) and platform-based design methodologies. Partitioning decreases the problem size to levels where each partition can be handled in realistic computational times. Accounting for timing during partitioning facillitates early wire planning, which in turn can lead to efficient area implementations as well as better performance. We present statistical timing driven hMetis-based partitioning. We approach timing driven partitioning from a different perspective: we use a statistical timing criticality concept to change the partitioning process itself. We exploit the hyperedge coarsening scheme of the hMetis partitioner for our timing minimization purpose. This allows us to perform partitioning such that the most critical nets in the circuit are not cut and therefore timing minimization can be achieved. The use of the hMetis partitioning algorithm makes our partitioning methodology faster than previous approaches. Integration of our partitioning algorithm into Capo placement tool demonstrates the ability of the proposed edge weighting approach for partitioning to lead to better circuit performance.

Code available
Related papers: C4, C6

Reconfigurable Computing: Non-contiguous Linear Placement
We present efficient solutions for the non-contiguous linear placement of data paths for reconfigurable fabrics. A strip-based architecture is assumed for the reconfigurable fabric. A pre-order tree-expression or a general graph is placed in a strip, which can have active and/or inactive pre-placed cores representing blockages and/or cores available for reuse. Two very efficient algorithms are proposed to solve the simpler problem of non-contiguous placement with blockages but without core reuse for tree graphs. The linear ordering obtained with any of the above algorithms is used as input for a third efficient algorithm to solve the problem of non-contiguous placement with both active and inactive cores. A fourth algorithm is proposed to solve the problem of non-contiguous placement with both core and connectivity reuse.

Code available
Related papers: W9


Power Optimization: Physical Design Level
It is intuitive that different placements will lead to different power consumption and thermal distribution patterns. A good placement can have a significant impact on power. We are currently working on efficient techniques so that high-activity nets are placed and routed such that the average and maximum power consumption is minimized while the thermal distribution is flattened.



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