Publications
S13	Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh, "HARP: Hardwired Routing Pattern FPGAs", International Symposium on Field Programmable Gate Arrays (FPGA), 2005.
S12	C. Ababei, H. Mogal, and K. Bazargan, "3D FPGAs: Placement, Routing and Architecture Evaluation", International Symposium on Field Programmable Gate Arrays (FPGA), 2005.
C11	C. Ababei, H. Mogal, and K. Bazargan, "Three-dimensional Place and Route for FPGAs", Asia and South Pacific Design Automation Conference (ASP-DAC), 2005.
C10	C. Ababei, P. Maidee, and K. Bazargan, "Exploring Potential Benefits for 3D FPGA Integration", Field Programmable Logic and its Applications (FPL), 2004.
W9	C. Ababei and K. Bazargan, "Non-Contiguous Linear Placement for Reconfigurable Fabrics", Reconfigurable Architectures Workshop (RAW), 2004.
C8	C. Ababei and K. Bazargan, "Placement Method Targeting Predictability Robustness and Optimality", Proc. ACM/IEEE International Conference on Computer-aided Design (ICCAD), 2003, pp. 81-85. | .ppt |
C7	P. Maidee, C. Ababei, and K. Bazargan, "Fast Timing-driven Partitioning-based Placement for Island Style FPGAs", Proc. ACM/IEEE Design Automation Conference (DAC), 2003, pp. 598-603. | .ppt |
C6	C. Ababei and K. Bazargan, "Timing Minimization by Statistical Timing hMetis-based Partitioning", International Conference on VLSI Design, 2003, pp. 58-63.
C5	C. Ababei, N. Selvakkumaran, K. Bazargan, and G. Karypis, “Multi-objective Circuit Partitioning for Cutsize and Path-based Delay Minimization”, Proc. ACM/IEEE ICCAD, 2002, pp. 81-85. | .ppt |
C4	C. Ababei and K. Bazargan, "Statistical Timing Driven Partitioning for VLSI Circuits", Proc. ACM/IEEE Design, Automation and Test in Europe Conference (DATE), 2002.
C3	C. Ababei and R. Marculescu, "Low-Power Realizations of Secure Chaotic Communication Schemes", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2000.
C2	C. Ababei, R. Marculescu , and V. Sundarajan, "Probabilistic Aspects of Crosstalk in CMOS ICs", IEEE Custom Integrated Circuits Conference (CICC), 2000.
C1	Radu Marculescu and Cristinel Ababei, "Improving Simulation Efficiency for Circuit-Level Power Estimation", IEEE International Symposium on Circuits and Systems (ISCAS), 2000.

	Poster presentations
P2	Cristinel Ababei: TPR: Three-D Place and route for FPGAs. FPL PhD Forum. Antwerp, Belgium, Sept. 2004. | .ppt |
P1	Cristinel Ababei: Multi-objective Circuit Partitioning for Cutsize and Path-Based Delay Minimization. SIGDA PhD Forum at DAC. San Diego CA. June 2004. | .ppt |

	Theses
T4	Cristinel Ababei, "Design Automation for Physical Synthesis of VLSI Circuits and FPGAs", Ph.D. Thesis, 2004.
T3	Cristinel Ababei, "Statistical Timing Driven Partitioning", M.S. Thesis, 2002.
T2	Cristinel Ababei, "Chaotic Communication Schemes", M.S. Thesis, 1998.
T1	Cristinel Ababei, "Design and Implementation of Low-voltage Low-power Current-mode Current Amplifier", B.E. Project, 1996.

	Publications from a previous life:
C8	C. Ababei and M. Derevlean, "On Passive Overunity-gain Network Synthesis and their Use into Oscillators", SCS99, Iasi / Romania, July 1999.
C7	M. Derevlean, L. Turic, and C. Ababei, "On the Amplitude Stability of the Most Common Amplitude Limiting Networks", SCS99, Iasi / Romania, July 1999.
C6	C. Orita and C. Ababei, "Isolated Gate Driving Circuit for High Power Switching MOSs", SCS99, Iasi / Romania, July 1999.
J5	C. Orita and C. Ababei, "Control Circuit for Forcing the Uninterrupted Optimum Regime in the Inductive Transfer DC-DC Converters", Iasi Polytechnic Institute Bulletin, Romania, 1999.
J4	C. Orita and C. Ababei, "Isolated Base Drive Control Circuit for High Power Switching BJTs", Iasi Polytechnic Institute Bulletin, Romania, 1999.
J3	C. Orita and C. Ababei, "Isolated Gate Drive Control Circuit for High Power Switching Devices", Iasi Polytechnic Institute Bulletin, Romania, 1999.
C2	M. Derevlean and C. Ababei, "A New Method for Electrolytic Capacitors Measuring", ETC98, Timisoara / Romania, Sept. 1998.
C1	C. Orita and C. Ababei, "Full Controlled DC-DC Converter with Capacitive Load", JSAEM, Japan, Nov. 1998.

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