HOME
FORUM
LINKS
DOWNLOAD
FAQ
CONTACT
Register now
Login
Main Menu
Home
News
Comics
Headlines
Forum
Tutorials
FAQ
Downloads
Web Links
Polls
Weather
Contact Us
Tutorials
Cadence
Synopsys
Forum
New Posts
Unread Topics
All topics
Who's Online
5
user(s) are online (
1
user(s) are browsing
FAQ
)
Members: 0
Guests: 5
more...
Top Posters
1
jgrad
179
2
svchw
29
3
ashkan2000
20
4
ebrunvand
20
5
jw4
11
6
pepet
9
7
vkundur
8
8
niliev
8
9
jamesstine
7
10
tikkir
7
FAQ
Categories
Cadence
What is OpenAccess
How do I decrease the core utilization in Silicon Ensemble?
I am trying to verify a layout with pads but no sucess
How do I decrease core utilization in Encounter?
How do I create an .io file for pad placement?
How to run static power analysis Encounter?
How can I tell Encounter to not open a GUI Window?
How can I use irsim to simulate my digital Cadence schematic?
Why does Abstract not support the "-tech" switch?
How to set the line thickness of waveform plots?
Synopsys
Why does Pathmill think my capacitors are floating?
OSU Cell Library
The layouts look like they are for Magic only. Can I use Cadence Virtuoso?
Can I add new cells? What tools do I need?
I am confused about the stacked vias in the AMI 0.5u library!
Freeware Tools
How can I get irsim to generate the clock for me?
How do I use vectors in irsim
How can I quickly create irsim test vectors?
Foundry PDKs
Verilog HDL
How do I specify combinational logic in Verilog?
How can I specify a regist with enable pin?
Do you have an example of a FSM?
General tools
How do I use VNC?
Why does the backspace key not work in Emacs?
My Linux or Cygwin command line is no good in Solaris!
Copyright © 2004 by
chiptalk.org
| Powered by XOOPS 2.0 © 2001-2003
The XOOPS Project
| Design by
7dana.com