ITC'99 Benchmark Submission Form

Use this form to submit information about a benchmark you might be interested in submitting. Please note the following:

Contact Information

Name:

Company or University:

Email:

Phone:

Format Information

In what languages is the RTL for your circuit available?


Verilog
VHDL
Other or Proprietary HDL
Please specify:
RTL not available


In what format is your gate level netlist?


Verilog
VHDL
EDIF
Vendor Specific Netlist Format (Please specify):
Other (Please specify):
Netlist not available


Do you have translators available to allow you to submit additional formats?
Yes.
From what to what?
No.

Cell Libraries

Please indicate which cell library is used in your design.

Verilog Cypress Hitachi
HP IBM LG Semiconductor
LSI Logic Lucent Mitsubishi
Motorola National Semiconductor NEC
Oki Philips SGS Thomson
Sharp Symbios Texas Instruments
Toshiba VLSI Technology Fujitsu

Other

My apologies for anyone I missed. Please send additions.


Design Details

All of the information above can be rough estimates, and is needed to ensure that we have a good distribution of benchmarks.

Design Size


Please estimate the size of your design in:
Gates:

Flip-flops and Latches:

Transistors:

How many Inputs Outputs and IOPuts are there in your design?

Features

Which of these features does your design have?

Embedded RAM, ROM, etc.
Internal tristate busses
Multiple Clock Domains
IP Cores.
Custom logic such as pass gate muxes, dynamic logic, etc.
Other Interesting Features: (Please list)

Are there functional vectors available for this design?
Yes. No.

Is DFT already included in this design (besides boundary scan)?
Yes. No.

Thank you!


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Scott Davidson
Last modified: Wed Jun 24 11:23:10 PDT