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Home > Technology Center > Parallel I/O Print This Page E-mail This Page Parallel I/O Altera provides a comprehensive I/O interface solution with support for a variety of single-ended and differential I/O standards, external memory, and high-speed interfaces to meet users' high-bandwidth system requirements. Stratix® II FPGAs Source-Synchronous Signaling Source-Synchronous Protocols Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix GX FPGAs  Source-Synchronous Signaling Source-Synchronous Protocols System Applications Single-Ended I/O Standards External Memory Device Interfaces On-Chip Termination Stratix FPGAs  Differential & Single-Ended I/O Standards High-Speed Interfaces External Memory Device Interfaces On-Chip Termination Cyclone™ II FPGAs  Cyclone II I/O Support Cyclone II Interfaces & Protocol Support External Memory Device Interfaces On-Chip Termination Cyclone FPGAs  Differential & Single-Ended I/O Standards External Memory Device Interfaces Quartus® II Software SPI-4.2 RapidIOâ„¢ Standard HyperTransportâ„¢ Standard Communications IP Cores Interfaces & Peripherals IP Cores DSP IP Cores Embedded Processors IP Cores Communication Standards Consortium Interfaces & Peripherals Standards Consortium DSP Standards Consortium Bus & I/O Design Examples I/O Standards & Interfaces Literature IP Communications Literature Interfaces & Peripherals Literature Altera® Technical Training Courses Fundamental Design Techniques for Stratix Devices Advanced Design Techniques for Stratix Devices Designing with Cyclone and Cyclone II Devices Stratix GX Solutions Stratix I/O Interface Solutions Board Design Guidelines Solution Center On-Line Technical Support Find Answers Database   Rate This Page

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