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Home > Products > Intellectual Property > Embedded Processors > Nios > Overview Print This Page E-mail This Page Nios Embedded Processor Overview The first-generation Nios® embedded processor is a user-configurable, 16-bit instruction set architecture (ISA), general-purpose RISC embedded processor that was designed to be an extremely flexible and powerful processor solution. The Nios processor's ease-of-use and flexibility has helped it become one of the world's most popular embedded processors; it has thousands of paying licensees. Designers needing higher processor performance, a smaller FPGA footprint, or more robust software development tools can take advantage of the Nios II embedded processor family. Embedded designers can use the SOPC Builder system development tool to very easily create custom processor-based systems. SOPC Builder can be used to integrate one or more configurable Nios CPUs with any number of standard peripherals, gluing the system together with the automatically generated Avalonâ„¢ switch fabric. The Nios embedded processor is optimized for Altera® programmable logic and system-on-a-programmable-chip (SOPC) integration. A user can easily combine the Nios processor with user logic and program it into an FPGA using SOPC Builder. The Nios processor is available in a portfolio of development kits. The configurable Nios CPU (with either 16- or 32-bit data path) is at the heart of a Nios processor-based system, and it can be configured for a wide range of applications. For example, a 16-bit-data-path Nios CPU running a small program out of on-chip ROM (on-chip memory blocks can be configured as ROM) makes an effective sequencer or controller and can take the place of a hard-coded state machine. Another example is a 32-bit data path Nios CPU with streaming peripherals, hardware acceleration units, and custom instructions, which is a powerful 32-bit embedded processor system. The Nios embedded processor differs from other soft-processor solutions in the market by featuring unique benefits such as custom instructions and the simultaneous multi-master Avalon switch fabric. These features allow Nios processor users to accelerate and optimize their designs by using simple yet non-traditional methods. More information about system acceleration using these features is available on the Nios processor literature web page. Table 1 shows a comparison of the 32-bit and 16-bit Nios embedded processors in typical configurations. Table 1. Comparison of Typical Nios Processor Configurations Feature 32-Bit Nios CPU 16-Bit Nios CPU Data bus size (bits) 32 16 Arithmetic logic unit (ALU) width (bits) 32 16 Internal register width (bits) 32 16 Address bus size (bits) 32 16 Instruction size (bits) 16 16 Logic elements (LEs) (typical) (1) Fewer than 1,400 Fewer than 1,000 fMAX (1) Over 180 MHz Over 180 MHz Note: Performance varies based on the target device architecture. The Nios embedded processor instruction set architecture is designed to provide the following elements: Efficient implementation in Altera FPGAs Minimum logic element (LE) usage Minimum memory usage Maximum clock speed Effortless system integration using SOPC Builder Simple memory interface Library of standard configurable peripherals Automatically generated Avalonâ„¢ switch fabric interface logic between CPUs, peripherals, and memory Optimized instruction-set architecture for compiled embedded software Flexible addressing modes Efficient use of large internal register file Quick interrupt handling Hardware acceleration blocks Effective algorithm implementation MSTEP instruction—single bit per cycle multiplication unit MUL instruction—fast integer multiplication unit Custom instructions Device Support The Nios embedded processor supports Altera's entire family of mainstream FPGAs. Table 2 lists the supported devices. Table 2. Nios Embedded Processor Device & Software Support Devices Design Software Description Stratix™ II Quartus II Highest-performance, highest-density, feature-rich platform with extensive memory resources Stratix High-performance, high-density, feature-rich platform with extensive memory resources Stratix GX High-performance architecture with high-speed serial transceivers Cycloneâ„¢ Low-cost ASIC replacement–suitable for price-sensitive applications APEXâ„¢ II High-density, high-performance platform with high-speed differential I/O standard support Mercuryâ„¢ High-performance, high-bandwidth, medium density platform that includes clock-data recovery (CDR) support Excaliburâ„¢ High-performance, hard processor core solution APEX 20K APEX 20KE APEX 20KC High-performance, medium- to high-density platform FLEX®  10K FLEX 10KE Low-cost, low- to medium-density platform ACEX® 1K Low-cost, low- to medium-density platform HardCopyâ„¢ High-density, high-volume ASIC alternative Rate This Page

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