IP CertificationsAltera is committed to providing intellectual property (IP) cores that work seamlessly with Altera® tools or interface specifications, providing a complete system-on-a-programmable-chip (SOPC) solution quickly and easily. To help you identify appropriate IP cores, Altera may award IP cores one or more of the following certifications.  | | Altera awards the AMPPSM Approved certification to all third-party IP cores that have been fully optimized for Altera devices and have undergone Altera's thorough internal review process. |
 | Altera awards the SOPC Builder Ready certification to IP cores that have plug-and-play integration with SOPC Builder, part of Quartus® II software. SOPC Builder Ready cores support interfaces for the Avalon™ switch fabric for the Nios® II embedded processors or advanced high-performance (AHB) ARM® on-chip bus, and include software drivers, low-level routines, or other software design files. Refer to the SOPC Builder Ready web page for more information about SOPC Builder Ready IP cores.
 | | Altera awards the DSP Builder Ready certification to IP cores that have plug-and-play integration with Altera's DSP Builder software. DSP Builder shortens digital signal processing (DSP) design cycles by helping you create the hardware representation of a DSP design in an algorithm-friendly development environment. You can combine existing MATLAB/Simulink blocks with Altera DSP Builder/MegaCore® blocks to verify system-level specifications and generate hardware implementations. After installing DSP Builder Ready IP, a symbol appears in the Simulink library browser under Altera DSP Builder blockset. |
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 | | Altera awards the Atlanticâ„¢ Compliant certification to IP cores that have an interface that is compliant with the Atlantic interface specification, a high-performance point-to-point interface for asynchronous cell- or packet-based transfers. The standard Atlantic interface makes it easy to integrate multiple IP cores and user-designed logic, potentially saving weeks of design time. |
 | | Altera awards the interoperability-tested, or I-Tested, certification to MegaCore or AMPP IP that has been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the necessary protocols. Refer to the I-Tested web page for more information about I-Tested IP cores. |
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