About AMPP Program As programmable logic device (PLD) density continues to increase, Altera Corporation recognizes that designers require design tools that will increase their productivity and allow them to keep pace with the increasing capacity of PLDs. A design methodology that uses pre-built megafunctions offers this productivity increase. The successful development of megafunctions requires close cooperation between intellectual property (IP) developers and PLD vendors. The Altera Megafunction Partners Program, or the AMPPSM program, was established in August 1995, to bring the advantages of megafunctions to Altera® PLD users.
The AMPP program identifies megafunction developers, trains them on Altera device architectures and tools, and promotes partners' solutions through Altera's broad marketing and sales channel. Altera does not participate in the licensing or delivery of AMPP megafunctions; the actual delivery and licensing of megafunctions is between the designer and the AMPP partner. Altera carefully selects each AMPP partner; continuing participation in AMPP is subject to the partner's active involvement in developing new megafunctions. By recruiting an active, diverse group of participants, Altera provides the widest range of megafunctions while minimizing product overlaps. An AMPP partner must meet at least two criteria: - Be large enough to handle Altera's world-wide business
- Have a roadmap of future megafunction products
AMPPSM partners are also required to attend training sessions provided by Altera, and are encouraged to re-attend future training sessions. Partners are instructed on how to develop megafunctions and to support encrypted megafunctions in the field. AMPP partners and the Altera sales staff work together closely to establish relationships with customers and to provide timely resources during megafunction evaluation and implementation. About AMPP MegafunctionsAMPP megafunctions are optimized for specific Altera device architectures. This optimization process usually involves setting compilation and synthesis options that maximize density and performance. AMPP megafunctions are then fine-tuned until they are as fast and small as possible. Figure 1 illustrates the typical process for evaluating, licensing, and using AMPP megafunctions. 
Using AMPP MegafunctionsAMPP megafunctions can be parameterized, programmed, and/or customized. Parameterizable megafunctions can be changed during design processing by setting options in the MAX+PLUS® II or Quartus® II software. Programmable megafunctions can be configured "on-the-fly," which changes behavior or specific function settings (e.g., a shift register with a dynamically adjustable maximum depth). AMPP partners modify customizable megafunctions to create new versions. Megafunctions that are customized may be included in the quoted license fee, but are typically subject to additional modification/consulting fees. Available FormatsAll AMPP megafunctions are available in post-synthesis AHDL format, a fully minimized and optimized netlist that can be used without risk of changes during design processing. Although VHDL and Verilog HDL files are available from most partners, a source code license is usually more expensive than a post-synthesis netlist license because the source code versions represent more intrinsic value. Altera recommends using post-synthesis netlists to avoid synthesis variation issues during design processing. This method ensures that no engineering effort is required to re-optimize the behavioral source code. OpenCore FeatureThe Altera MAX+PLUS II and Quartus II software provide the OpenCore® feature, which allows the designer to evaluate the megafunction prior to purchasing the license. The OpenCore feature allows the designer to compile the megafunction and determine the megafunction's size and speed, but it prevents the designer from generating programming files. This feature allows AMPP partners to offer OpenCore evaluations without risking licensing interests. Megafunctions in the Design FlowAMPP megafunctions are intended as "drop-in" design elements for design flows supported by the MAX+PLUS II and Quartus II software. Although the megafunctions are developed as stand-alone functions, they can be integrated with other megafunctions and logic in a top-down design methodology. The ideal design flow assesses a project's functional block requirements and assigns megafunctions to implement different portions of a system. Once the megafunction blocks are defined, designers can focus on design elements that cannot be sourced as megafunctions or that are proprietary features of the system. AMPP megafunction support extends to third-party design flows that are currently supported by Altera tools. For design flows that use standard EDA tools, designers can instantiate AMPP megafunctions in a design by specifying the cell and port names in an HDL design file. For design flows that are entirely within the MAX+PLUS II software, the designer can use the megafunction in a Graphic Design File (.gdf), AHDL™ Text Design File (.tdf), or VHDL Design File (.vhd). During design, the EDA tool passes the megafunction's cell and port names into the EDIF file. Assuming that a downstream processing tool will replace the cell name with the actual functional specification, the EDA tool will not process beyond the name level. Once the megafunction is part of a the MAX+PLUS II software project hierarchy, the designer must specify three synthesis options before the megafunction is processed by the MAX+PLUS II software: - Assign the megafunction to a clique, which ensures that the placement of the megafunction is optimized for high performance.
- Assign the WYSIWYG logic synthesis style, which tells the MAX+PLUS II software to turn off logic synthesis when it processes the megafunction.
- Apply any top-level timing assignments provided by the AMPP partner to the hierarchy before design processing.
For information on cliques, logic synthesis styles, and instantiating functions, go to MAX+PLUS II Help. During compilation, the MAX+PLUS II software recognizes the megafunction as an AMPP megafunction and verifies that a valid megafunction license exists. MAX+PLUS II then completes design processing according to the permissions granted by the AMPP megafunction license. Performance & Density SpecificationsThe performance and density specifications in this catalog apply to megafunctions compiled as stand-alone designs. Additional logic synthesis may affect the performance or density of a megafunction, particularly when the function is combined with other megafunctions or logic. Megafunctions shipped as post-synthesis AHDL files have minimal performance or density variations, because additional design processing is not required. Megafunctions supplied as behavioral source code files may experience changes in performance or density, depending on the design and the target device. Timing cannot be determined until synthesis and placement of the final design is complete. Each AMPP megafunction has a performance metric that provides performance information when the megafunction is compiled as a stand-alone project. The metric is usually a global clock speed or fMAX, but in some cases, other metrics such as a propagation delay or sample/second is given. The global clock setup time (tSU) and global clock-to-output (tCO) delay are also useful parameters. Contact the AMPP partner to determine which additional performance metrics are available for the megafunction. In general, a global clock frequency is not affected by the I/O delays that route the signal off-chip, whereas on-chip and off-chip routing directly impact the tSU and tCO parameters. If a megafunction is integrated with other logic or megafunctions on the same device, the set-up and clock-to-output delays will be reduced because off-chip/on-chip delays are not required. Subsequent versions of the MAX+PLUS II and Quartus II software, megafunction design modifications, or the availability of faster speed-grade devices may affect density or performance characteristics. Contact the AMPP partners for the latest megafunction specifications. AMPP Megafunction Package ContentsAn AMPP megafunction package typically contains the following items (items that accompany every package are highlighted in blue): - Megafunction license
- Megafunction design file (typically a post-synthesis netlist)
- Symbol File (.sym) for use in MAX+PLUS II GDFs
- Include File (.inc) for use in MAX+PLUS II TDFs
- VHDL and Verilog HDL instantiation templates
- Megafunction documentation
- Top-level timing assignments
- Help file (typically in HTML)
- Simulation stimulus file(s)
AMPP partners have different levels of support and documentation. Designers should contact the AMPP partner directly to ensure that appropriate support will be provided. Most partners will supply more sophisticated simulation information, such as pre-synthesis bus simulation models for use in third-party logic synthesis tools, prior to processing in the MAX+PLUS II software. Licensing AMPP MegafunctionsAMPP megafunction are licensed directly from AMPP partners. The terms and conditions for the license of each AMPP megafunction may vary from partner to partner. Each AMPP partner typically specifies the megafunction licensing terms based on the needs of the end user. AMPP megafunction license options may include: - Duration of the license (e.g., lifetime, 1 year, or 6 months)
- Source-code access
- OpenCore feature
AMPP megafunction licenses generally limit the use of the licensed AMPP megafunctions to PLDs from Altera. Permission should be received, in writing, from the AMPP partner before an AMPP megafunction is used in a target device other than an Altera PLD. Using an AMPP megafunction in a PLD allows customers to take this IP core to a high-volume, low-cost HardCopyâ„¢ device with relatively low additional license and/or fee payments to the AMPP partner. Choosing to use an AMPP megafunction in an ASIC, gate array, or non-Altera PLD and would require full additional license and/or fee payments to the AMPP partner. The duration of an AMPP megafunction license typically defines the period of time during which the AMPP megafunction may be compiled as part of a project in MAX+PLUS II. Once the programming file for an Altera PLD has been created, AMPP megafunction licenses generally convey unlimited lifetime manufacturing rights to use the licensed megafunction in Altera PLDs as incorporated in the programming file. Any limitations in the use of the licensed megafunction may vary from partner to partner. To protect the embedded intellectual property (IP), AMPP megafunctions are typically shipped as encrypted files. Although the megafunction design file will have a standard filename (e.g., function.tdf), the file will appear corrupted when opened with a text editor. The encrypted megafunction design file is actually a binary file. Access authorization and decryption are handled by MAX+PLUS II, which uses a megafunction authorization code generated and supplied by the AMPP partner. AMPP megafunction licenses use the same authorization process as the MAX+PLUS II software. PC/Windows installations of the MAX+PLUS II software use an embedded license system, based on the serial number of the MAX+PLUS II software guard (guard ID). Workstation installations of the MAX+PLUS II software use the FLEXlm license manager and treat each AMPP megafunction as a new MAX+PLUS II feature. Workstation licensing can either be locked or floating node, depending on the licensing partner's policy. AMPP partners supply AMPP megafunctions licenses. Altera does not have the ability to generate any license for any AMPP megafunction. AMPP Megafunction PricingDesigners should contact the appropriate AMPP partner for a price quote or estimate on a megafunction license. To help determine the cost of a megafunction license and to ensure that the megafunction successfully integrates with the end application, be prepared to provide the AMPP partner with the following information: - Relevant megafunction parameters (e.g., bus width, resolution)
- License duration requirements (e.g., lifetime, 6 months)
- Target device architecture (e.g., FLEX 10K, MAX® 9000)
- Netlist-only or source-code license
- Any requirements for modifications or feature changes
- Any requirements for design migration (e.g., to a HardCopy device, gate array, or ASIC)
Technical SupportAMPP megafunctions are carefully developed by AMPP partners to ensure the highest possible quality. If a problem is traced to a megafunction, the AMPP partner is responsible for resolving the problem. If a problem arises with integrating the megafunction with other logic, Altera will provide appropriate engineering support. WarrantyThe megafunctions in this catalog, as well as other megafunctions and services available from the AMPP partners, are provided without warranty by Altera. Altera expressly disclaims all warranties, express and implied, with respect to the megafunctions supplied by the AMPP partners, including, but not limited to, implied warranties of merchantability, fitness for a particular purpose, title and non-infringement. The AMPP partners may offer guarantees or warranties for design performance or functionality; contact the individual AMPP partners for details. Contact AMPPTo suggest products that you would like to have implemented as megafunctions, or for comments or questions about AMPP, please send e-mail to ampp-info@altera.com. To find out more about becoming an AMPP member, please send e-mail to ampp-manager@altera.com. | 
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