Research assistantships and post-doctoral positions are available. Available projects are in the areas of: (1) the MARCO Gigascale Silicon Research Center's "core pillar" (system-level roadmapping); (2) VLSI physical design spanning interconnect design, large-scale partitioning and placement, and problems at the VLSI design-manufacturing interface; (3) STARC-sponsored research on back end of the line (BEOL) CMP modeling, interconnect/fill extraction, and intelligent fill synthesis flows, as well as on noise-aware statistical timing and lithography hotspot filtering; and (4) an NSF project on manufacturing-aware physical design.