MARCO GSRC Calibrating Achievable Design: Bookshelf

Verilog Links and Tools

(see other slots)

Disclaimer: the links below may point to sites that are not part of the MARCO/GSRC bookshelf. Such sites typically distribute design information under their own copyright and license agreements that are different from those of the MARCO/GSRC bookshelf. The links below imply neither containment in the bookshelf nor endorsement.

Verilog FAQ

VeriPool

lists public domain parsers and other resources

Verilog to HTML converter

Home page (saves a lot of useful info; the parser can be used separately)

VexTools (including a free Verilog parser)

Home page

Verilog parser in C

from Mike Riepe and Matt Guthaus at U.Mich

Verilog parser in PERL

CPAN module

Verilog-to-[flat]BLIF translator

from Mike Riepe at U.Mich

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