BEGIN CLASSCONSTRAINTS
BEGIN CLASS2CLASS < MAXDELAY delay> < MINDELAY delay> < MAXLENGTH length> 
   < MINLENGTH length>
< INPUTSLEW < delay>>
BEGIN OUTPUTS
nodeId pinId
nodeId pinId
nodeId pinId
END OUTPUTS
BEGIN INPUTS
nodeId pinId
nodeId pinId
nodeId pinId
END INPUTS
END CLASS2CLASS

BEGIN CLASS2CLASS < MAXDELAY delay> < MINDELAY delay> < MAXLENGTH length> 
   < MINLENGTH length>
< INPUTSLEW < delay>>
BEGIN OUTPUTS
nodeId pinId
nodeId pinId
nodeId pinId
END OUTPUTS
BEGIN INPUTS
nodeId pinId
nodeId pinId
nodeId pinId
END INPUTS
END CLASS2CLASS

END CLASSCONSTRAINTS
// A CLASS2CLASS timing constraint specifies one or more of
// a maximum path delay, a minimum path delay, a maximum path length,
// a minimum path length and a noise margin (specified as a fraction 
// between 0 and 1 of the voltage difference between supply and ground),
// between equivalence classes of start and end pins of timing paths.
// The noise margin applies to all receiver (input) pins on all timing paths.
// A timing path is any purely combinational (i.e., does not
// pass through a sequential cell) pin-to-pin-to-pin... path from 
// a starting output pin to an ending input pin.
// Delay is expressed in seconds.   Length is expressed in database units.
// Delays should be evaluated for both rising and falling inputs at the
// start of the path. If INPUTSLEW is specified, then this applies to
// the signal transition at the input of the path. 


BEGIN EXPLICITCONSTRAINTS
BEGIN EXPLICITPATH < MAXDELAY delay> < MINDELAY delay> 
< MINRISE rise> < MINFALL fall> 
< MAXLENGTH length> < MINLENGTH length> < NOISEMARGIN noise>
< INPUTSLEW < delay>>
pinID [nodeName]
pinID [nodeName]
pinID [nodeName]
pinID [nodeName]
...
END EXPLICITPATH 

BEGIN EXPLICITPATH < MAXDELAY delay> < MINDELAY delay> 
< MINRISE rise> < MINFALL fall> 
< MAXLENGTH length> < MINLENGTH length> < NOISEMARGIN noise>
< INPUTSLEW < delay>>
pinID [nodeName]
pinID [nodeName]
pinID [nodeName]
pinID [nodeName]
...
END EXPLICITPATH 

END EXPLICITCONSTRAINTS
// An EXPLICITPATH timing constraint specifies one or more of
// a maximum path delay, a minimum path delay, a maximum path length,
// a minimum path length for an explicitly defined timing path, and a 
// noise margin (specified as a fraction between 0 and 1 of the voltage
// difference between supply and ground). 
// Such a timing path passes through an ordered list of pins in the netlist. 
// The noise margin applies to all receiver (input) pins on the timing path.
// Delay is expressed in seconds.   Length is expressed in database units.
// Delays should be evaluated for both rising and falling inputs at the
// start of the path. If inputSlew is specified, then this applies to
// the signal transition at the start of the path (i.e., the driving
// gate output). 
// Note that this is sufficient for single steiner topology synthesis
// by specifying just two pins.


BEGIN NETBOUNDS 
< netName> [MAXLENGTH length] [MAXCAP capacitance]
< netName> [MAXLENGTH length] [MAXCAP capacitance]
< netName> [MAXLENGTH length] [MAXCAP capacitance]
< netName> [MAXLENGTH length] [MAXCAP capacitance]
< netName> [MAXLENGTH length] [MAXCAP capacitance]
END NETBOUNDS 

// MAXLENGTH is in database units (see .tech file).   MAXCAP is in
// farads.   These are bounds on the interconnect tree (with sink inputs)
// driven by a given gate output (source).    These bounds are typically
// applied for performance (e.g., timing-driven placement) or reliability
// (e.g., electromigration, hot-electron, self-heat) considerations.