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Journal

[1] Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi and D. M. H. Walker, "A Circuit Level Fault Model for Resistive Bridges," ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 8, No. 4, Oct. 2003, pp. 546-559.

[2] Weiping Shi and Zhuo Li, "A Fast Algorithm for Optimal Buffer Insertion," IEEE Transactions on Computer-Aided Design (TCAD), Vol. 24, No. 6, June 2005, pp. 879-891. (2007 IEEE Circuits and Systems Society Outstanding Young Author Award)

[3] Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, and Weiping Shi, "Longest Path Selection for Delay Test under Process Variation," IEEE Transactions on Computer-Aided Design (TCAD), Vol. 24, no. 12, December 2005, pp. 1924-1929.

[4] Zhuo Li and Weiping Shi, "An O(bn²) Algorithm for Optimal Buffer Insertion with b Buffer Types," IEEE Transactions on Computer-Aided Design (TCAD), Vol. 25, no. 3, March 2006, pp. 484-489.

[5] Zhuo Li, Ying Zhou and Weiping Shi, "Wire Sizing for Non-Tree Topologies," IEEE Transactions on Computer-Aided Design (TCAD), Vol. 26, No. 5, May 2007, pp. 872-880.

[6] Charles J. Alpert, Shrirang Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, C. N. Sze, Paul G. Villarrubia, and Mehmet Yildiz, "Techniques for Fast Physical Synthesis," Proceedings of the IEEE, Vol. 95, No. 3, March 2007, pp. 573-599.

[7] Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang Karandikar, Zhuo Li, Weiping Shi and C. N. Sze, "Fast Algorithms for Slew Constrained Minimum Cost Buffering," IEEE Transactions on Computer-Aided Design (TCAD), Vol. 26, No. 11, November 2007, pp. 2009-2022.

[8] David A. Papa, Tao Luo, Michael D. Moffitt, C. N. Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov, "ISPD08: RUMBLE: An incremental, timing driven, physical-synthesis optimization algorithm," IEEE Transactions on Computer-Aided Design (TCAD), to appear

[9] Rouwaida Kanj, Zhuo Li, Rajiv Joshi, Frank Liu, and Sani Nassif, "Root-Fiding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations," IEEE Transactions on Semiconductor Manufacturing, Vol. 22, No. 1, Feb. 2009, pp. 22-30. (Invited extended version on special issue of ISQED).

[10] Shiyan Hu, Zhuo Li, and Charles J. Alpert, "A Fully Polynomial Time Approximation Scheme for Timing Constrained Minimum Cost Layer Assignment," IEEE Transactions on Circuits and Systems II, accepted.

Conference

[1] Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi and D.W. H. Walker, "A Circuit Level Fault Model for Resistive Opens and Bridges," 21st IEEE VLSI Test Symposium (VTS), Napa Valley, CA, April 27 - May 1, 2003, pp. 379-384.

[2] Zhuo Li, Xiang Lu and Weiping Shi , "Process Variation Dimension Reduction based on SVD," Proc. 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Bangkok, Thailand, May 25-28, 2003, Vol. 4, pp. 672-675.

[3] Weiping Shi and Zhuo Li, "An O(nlogn) Time Algorithm for Optimal Buffer Insertion," 40th Design Automation Conference (DAC), Anaheim, CA, June 2-5 2003, pp. 580-585.

[4] Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker and Weiping Shi, "CodSim - A Combined Delay Fault Simulator," 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Cambridge, MA, Nov. 3-5, 2003, pp. 79-86.

[5] Weiping Shi, Zhuo Li and Charles J. Alpert, "Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost," 9th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 27-30, 2004, pp. 609-614.

[6] Xiang Lu, Zhuo Li, Wangqi Qiu, Weiping Shi and D. M. H. Walker, "Longest Path Selection for Delay Test Under Process Variation," 9th Asian and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 27-30, 2004, pp. 98-103.

[7] Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H Walker and Weiping Shi, "PARADE: PARAmetric Delay Evaluation Under Process Variation," 5th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 22-24, 2004, pp. 276-280.

[8] Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker and Weiping Shi, "A Statistical Fault Coverage Metric for Realistic Path Delay Faults," 22nd IEEE VLSI Test Symposium (VTS), Napa Valley, CA, April 25-29, 2004, pp. 37-42.

[9] Wangqi Qiu, Jing Wang, Xiang Lu, Zhuo Li, D. M. H. Walker and Weiping Shi, "At-speed test for path delay faults using practical techniques," 2004 IEEE International Workshop on Current and Defect Based Testing, Napa Valley, CA, April, 2004, pp. 59-64.

[10] Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker and Weiping Shi, "A circuit level fault model for resistive MOS gate short," 5th International Workshop on Microprocessor Test and Verification, Austin, TX, 9-10 September, 2004, pp. 97-102.

[11] Wangqi Qiu, Jing Wang, D. M. H. Walker, D. Reddy, Xiang Lu, Zhuo Li, Weiping Shi and H. Balachandran, "K Longest Paths per Gate (KLPG) test generation for scan-based sequential circuits," International Testing Conference (ITC), Charlotte, NC, October, 2004, pp. 223-231.

[12] Zhuo Li, C. N. Sze, Charles J. Alpert, Jiang Hu and Weiping Shi, "Making fast buffer insertion even faster via approximation techniques," 10th Asia and South Pacific Design Automation Conference (ASP-DAC), ShangHai, China, Jan. 2005, pp. 13-18. slides.

[13] Zhuo Li and Weiping Shi, "An O(bn²) Time Algorithm for Optimal Buffer Insertion with b Buffer Types," Conference on Design, Automation and Test in Europe (DATE), Munich, Germany, March 7-11 2005, pp. 1324-1329. slides

[14] Sani R. Nassif and Zhuo Li, "A More Effective Ceff," 6th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 21-23, 2005, pp. 648-653.

[15] Zhuo Li and Weiping Shi, "An O(mn) time algorithm for optimal buffer insertion of nets with m sinks," 11st Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2006, pp. 320-325. slides

[16] Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang Karandikar, Zhuo Li, Weiping Shi and C. N. Sze, "Fast Algorithms for Slew Constrained Minimum Cost Buffering," 43rd Design Automation Conference (DAC), San Francisco, July 24-28, 2006, pp. 308-313.

[17] Mandar P. Waghmode, Zhuo Li and Weiping Shi, "Buffer Insertion in Large Circuits with Constructive Solution Search Techniques," 43rd Design Automation Conference (DAC), San Francisco, July 24-28, 2006, pp. 296-301.

[18] Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li and Weiping Shi, "A New RLC Buffer Insertion Algorithm," International Conference on Computer-Aided Design (ICCAD), San Jose, November 5-9, 2006, pp. 553-557.

[19] Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi and Frank Liu, "A new methodology for interconnect parasitics extraction considering photo-lithography effects," 12nd Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan 23-26, 2007.(Best Paper Award)

[20] Charles J. Alpert, Shrirang Karandika, Zhuo Li, Gi-Joon Nam, C. N. Sze, Stephen T. Quay, Haoxing Ren, Paul G. Villarrubia and Mehmet Yildiz, "The Nuts and Bolts of Physical Synthesis," 2007 International Worshop on System Level Interconnect Prediction (SLIP 07), Austin, Texas, March 17-18, 2007, pp. 89-93.

[21] Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin Sapatnekar and Weiping Shi, "Probabilistic congestion prediction with partial blockages," 8th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 26-28, 2007, pp. 841-846.

[22] Ying Zhou, Zhuo Li, Rouwaida N. Kanj, David A. Papa, Sani Nassif and Weiping Shi, "A More Effective Ceff for Slew Estimation," International Conference on IC Design & Technology, Austin, Tx, May 30 - June 1st, 2007, pp. 1-4.

[23] Ying Zhou, Zhuo Li and Weiping Shi, "A hybird BEM algorithm for capacitance extraction in multi-layer, comformal and embedded dielectrics," 44th Design Automation Conference (DAC), San Diego, CA, June 4-8, 2007, pp. 835-840.

[24] Rouwaida Kanj, Zhuo Li, Rajiv Joshi, Frank Liu and Sani Nassif, "A root-fiding method for assessing SRAM stability," 9th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 17-19, 2008, pp. 804-809. (Best Paper Nominee)

[25] David A. Papa, Tau Luo, Michael D. Moffitt, C. N. Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov, "RUMBLE: An incremental, timing driven, physical-synthesis optimization algorithm," International Symposium on Physical Design (ISPD), Portland, Oregon, April 13-16, 2008, pp. 2-9.

[26] Zhuo Li, Charles J. Alpert, Shiyan Hu, Tuhin Muhmud, Stephen T. Quay and Paul Villarrubia, "Fast Interconnect Synthesis with Layer Assignment," International Symposium on Physical Design (ISPD), Portland, Oregon, April 13-16, 2008, pp. 71-77.

[27] Michael D. Moffitt, David A. Papa, Zhuo Li and Charles J. Alpert, "Path Smoothing via Discrete Optimization," 45th Design Automation Conference (DAC), Anaheim, CA, June 8-13, 2008, pp. 724-727.

[28] Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, JB Kuang, Hung Ngo, Ying Zhou, Weiping Shi and Sani Nassif, "SRAM Methodology for Yield and Power Efficiency: Per-Element Selectable Supplies and Memory Reconfiguration Schemes," International Symposium on Low Power Electronics and Design (ISLPED), Bangalore, India, August 11-13, 2008, pp. 87-92.

[29] Shiyan Hu, Zhuo Li, Charlest J. Alpert, "A Polynomial Time Approximation Scheme for Timing Constrained Minimum Cost Layer Assignment," International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 10-13, 2008, pp. 212-215.

[30]Tao Luo, David Papa, Zhuo Li, C. N. Sze, Charles J. Alpert and David Z. Pan, "Pyramids: An Efficient Computational Geometry-based Approach for Timing-driven Placement," International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 10-13, 2008, pp. 204-211.. (Best Paper Nominee)

[31]Ying Zhou, Rouwaida Kanji, kanak Agarwal, Zhuo Li, R. Joshi, Sani Nassif, Weiping Shi, "The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield," 10th International Symposium on Quality Electronic Design (ISQED), San Jose, CA, March 17-19, 2009, pp. 607-612.

[32]Shiyan Hu, Zhuo Li, and Charles J. Alpert, "A Faster Approximation Scheme for Timing Driven Minimum Cost Layer Assignment," International Symposium on Physical Design (ISPD), San Diego, CA, March 29-31, 2009, pp. 167-174.

[33]Shiyan Hu, Zhuo Li, and Charles J. Alpert, "A Fully Polynomial Time Approximation Scheme for Timing Driven Minimum Cost Buffer Insertion," 46th Design Automation Conference (DAC), San Francisco, CA, July 26-31, 2009.

Patents (2 issued and 11 pending)

• Charles J. Alpert, Zhuo Li and Stephen T. Quay, "Techniques for Super Fast Buffer Insertion," US Patent 7,392,493.
• Charlest J. Alpert, Zhuo Li and Stephen T. Quay, "Probabilistic Congestion Prediction with Partial Blockages," US Patent 7299442.
  

Others

• Poem: For Mum, Editor's Choice Award (it seems not hard to get this award), April 2002, published in "Shells upon the Shore". Also available at poetry.com (The International Library of Poetry).
  

I found out that I have a paper published in a Chinese Journal submitted by my old colleague Qingyu based on my Master thesis work on WinCC communication with Simens product. It is interesing and this work should be counted as my first publication and only one written in Chinese (other than my Bachelor and Master Thesis). It is more like a user experience and application paper. My major back to that time is Control Automation and more on application side, i.e., instrumentation and measurement. It's quite fun to work in the industry and let things work as you want. :)

• Qingyu Yang, Zhuo Li and Ren Shi, "Implementation of Communication Between WinCC and Multiprocessor S5-135U PLC Using Profibus," Measurement & Control Technology, Vol. 21, No. 2, 2002, pp. 33-34, 36.