ELEN 689-607 VLSI Interconnect Modeling and Optimization
Spring 2005, Tu/Th 12:45-2:00pm, Richardson 208
INSTRUCTOR: Dr. Jiang Hu
Email: jianghu@ee.tamu.edu
Phone: 847-8768
Webpage: http://dropzone.tamu.edu/~jhu
Office: WERC 320G
Office hour: Tu/Th 2:30-3:30pm or by appointment
COURSE DESCRIPTION
When VLSI technology enters nanoscale regime, its progress faces several limiting factors: the fundamental interconnect limit, variational effect and sub-wavelength manufacturability. These represent emerging issues for next generation IC designs as well as new market area for electronic design automation. This course provides a comprehensive introduction on leading edge research results regarding these problems. In addition, basic modeling and optimization techniques are described simultaneously to equip students with necessary skills for handling nanometer VLSI designs.
TOPICS- Statistical timing analysis and optimization: statistical timing analysis considering correlations, statistical gate sizing, variation aware retiming.
- High speed interconnect design: buffer insertion, wire sizing, wire pipelining and wire retiming.
- Interconnect modeling: transmisson line model, crosstalk noise, inductance modeling, interconnect delay and slew metrics.
- Modern clock network synthesis: clock tree and non-tree layout, skew scheduling, clock mesh sizing and next generation clocking techniques such as rotary clock and resonant clock.
- Design for manufacturability: impact of sub-wavelength lithography, phase shifting mask compliance, optical proximity correction, antenna avoidance and chemical mechanical polishing.
- Basic optimization techniques: linear programming, nonlinear programming, dynamic programming, branch and bound, network flow and Lagrangian relaxation.
PREREQUISITE
Basic knowledge on digital design, circuit theory, algorithms and C/C++ programming, or consent of the instructor.
LECTURE AGENDA- Buffer insertion, (reading)
- Wire pipelining, (reading)
- Statistical timing analysis, (reading), (slides), (reference)
- Insights into fast physical synthesis, guest lecture by Dr. Alpert of IBM Austin Research Lab
- Asymptotic waveform evaluation (reading)
- Elmore and lognormal delay/slew model (reading)
- Capacitive crosstalk models (reading1), (reading2)
- Inductance (reading)
- Transmission line model
- Linear programming and application on skew scheduling (reading)
- Nonlinear programming and application on power supply network optimization (reading)
- Network flow and its application on routing (reading)
- Guest lecture by Dr. Chandramouli Kashyap from IBM (March 1, Tuesday)
- Midterm exam (March 3, Thursday)
- Combinatorial optimization
- Graph based skew scheduling (reading) and retiming (slides)
- Lagrangian relaxation (reading)
- Gate and wire sizing (reading)
- Crosstalk and antenna avoidance in layer assignment (reading)
- Cell placement (reading)
- Clock tree layout (reading)
- Non-tree clock network synthesis (reading)
- Rotary clock (reading) and resonant clock (reading)
- PSM compliant layout (reading1), (reading2)
- OPC friendly layout (reading)
- Guest lecture, Freescale (April 26, Tuesday)
- Chemical mechanical polishing
- Layout compaction
PROJECTS
Project 1, reference
Project 2, reference1 (slides), reference2
Project 3, reference
REFERENCES
- H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, Inc., 1990.
- Chung-Kuan Cheng, John Lillis, Shen Lin and Norman Chang, Interconnect Analysis and Synthesis, John Wiley & Sons, Inc., 2000.
- H. Johnson and M. Graham High Speed Signal Propagation: Advanced Black Magic, Pearson Education, 2003.
- C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization: Algorithms and Complexity, Dover Publications, Inc., 1998.
- A. K.-K. Wong, Resolution enhancement techniques in optical lithography, SPIE Press, 2001.
- Technical papers.
GRADING
Midterm 20%
Project 60%
Final take-home exam 20%